From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 895B21A2C0B for ; Wed, 29 Apr 2026 14:00:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777471209; cv=none; b=rlGZPlbYZ4sI1VCbVptMKr/GUNDdoe8S3JWnM9ZEDSba1lcmgPf2db3GfMiyZRHs1QH1x4GAxfkx3KIJ/xlSiHf4gQyPYTjs5WZY7IvZe0v5AKoWpbKTXZ7kbybxrahYu7Ah6K4A9BH57+cn946TtGweM3vA2nXgY247rV86ZqM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777471209; c=relaxed/simple; bh=uybU3a3N0n0+jby1CmvCwk1L1SefcxFqIYnY1BYddAM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VwOnq9vSlbVq6pERBi79Rv5mvymHoUBTkbHDxRfW+LzhTQQo4HjGg/MeB86ckFd0ALIIfiaXflLZnLJWhfBIAVwIm4BneylYiRpOvPwLNgx7747fCUvTfAGzL0jCQ9AtRveeNPsIT14I26Uup/7litlqMSq9fGolDd7vwM8arJk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mxkyfsFv; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mxkyfsFv" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4838c15e3cbso115861965e9.3 for ; Wed, 29 Apr 2026 07:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777471206; x=1778076006; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=pXYxfb1OnKvjy9v+vQDtCcuNHO3JiDi1MdrPDxdzPQ4=; b=mxkyfsFvPVBCUGLbQM+72bZVdnssX9Y05xc2sKUybW9xAr80jXDNfSTDWEBc9ERQzK xRCC7+HbSaDH3E1ZhIqdShw3xKz+b4gNCKt8Fil+TOxwDZvMWMDUn8TbJG4Zz/5J8a3e 4HtyqCkjWIFBsw119wcUumysVqAGQqahwKVcw00SjN8PeVD+9KgGKuF1XzIyG4PtLaX9 Vlmc8X3fdV6DDhnip+sQwp7g+TD8kSyUxXSAXjSEgiae8b2gtGab/KqJJD6EaVWkGMu1 hkBSFPPq8NO51el2QCMJCCkm1GxEcWfPNikhslB5Kvs8Dxdr82L5+JuLlFJF3k1YRlM6 niMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777471206; x=1778076006; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pXYxfb1OnKvjy9v+vQDtCcuNHO3JiDi1MdrPDxdzPQ4=; b=HBIOeTVDyvzO+OkVcJ7XlKZsoCJxPQhykZkHp1yYcg56Q27+DfuVwqOcAl722fUhhk NAi/62+WxCeoom3UY8kjaufGe0GQU/0MEiuPn2CQpntR2+0ep2bMcF+OQMCPh3N27jsh +fqwMXpKQoQZaV2QlWJEEk6DvOa4iNHAAX5nqqMqh3e8SnlBvk8P0Vj/O87kCLTeC7rf lC/N6kUMXw5htWqNSOdH4qE17TbqTE5cUKQRiK3qqoChrpYOf7/wNxjz2ynPTwtaq3Kh eNmZnuVxkz48DFrO97NnoVY9xPwrBEwdvE0QrKmYpSCwe16YfjzfBWb1ZekSOkqLtumC Gd9A== X-Forwarded-Encrypted: i=1; AFNElJ8FB+BEOOt3tw+1GP92uKTtswIJDbcu+WsD5fTSMMqBfQNp/N1oOkPqD/6WBQ5Wlr88R5yAqN/EB1wql85V@vger.kernel.org X-Gm-Message-State: AOJu0YweeX6qtlPJHJzM8JKMqlVoFAtRcMT3KbIbk8dzUysGL+yUkZ36 Z6X/vOa2Rva41fs2HzwRfjUN7DKMGWcNpQV94kEi54n2bNw6/4Xq5Hne X-Gm-Gg: AeBDiet7n76l8f4C7IHwUgnoLegAoVB5s9BeC72PqpH8ZtoajD9NOFRQ4DVqGGPyjB3 qnUec7aRo/q3uDGzQvjnpuCMyH0GMTFwnyKCUhZJ90M6XguvineL+VHCfNRvsC8jRPvVULMaxqc TBqcJOAbX9UnqDqWH0uTwmeNKufJ4YTleLwNbC/nKvoRejawGwIcste0mrRui6Qj3UD5JGclsRl XVgv4hayQjwGaMAbovqgIz3YoDwzh+LKohZOJK1FvZEvH5WrwjilmLxDxw7s6SuXNBUPKEn213V g4ow5Hpp2aBfo1INnYlJM6ap2dMixwL7sZuPkJhcVttZd6XbM7LSPdNOueBtJhxuMuUCpEDjLtn me8ogtiVq4jTfz9pHUzHLQ79DjEFYfqyyGxJApnRvS6GXkVrKKK2kJp4lyEBSAMJHn5Ugu2VnM5 KH0J6QhLmyOLZtzFMmOIehqHmoCAApnLeRZFNVLlN6YZV+BYAyTbsJw71I/mFIhN3KE9QLt8+Nj g== X-Received: by 2002:a05:600c:c048:b0:48a:6268:18a9 with SMTP id 5b1f17b1804b1-48a782dd8e3mr77937175e9.13.1777471202791; Wed, 29 Apr 2026 07:00:02 -0700 (PDT) Received: from ?IPV6:2a00:f502:160:68fe:a26c:adcb:8da8:2? ([2a00:f502:160:68fe:a26c:adcb:8da8:2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-447b4216eecsm5409919f8f.9.2026.04.29.07.00.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Apr 2026 07:00:02 -0700 (PDT) Message-ID: <05df6383-5325-4f88-9638-22bc2d7a768d@gmail.com> Date: Wed, 29 Apr 2026 17:00:00 +0300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 07/11] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled To: Konrad Dybcio , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Andr=C3=A9_Apitzsch?= , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org References: <20260427-msm8939-venus-rfc-v3-0-288195bb7917@gmail.com> <9kBbj8Jr-f6eqC6XfnJPf3gKQD-3WfzXgzl4KEVKhRZlW2_GftgFBsijqUgEvGcgmeFqPwtVquMmibHUMaR_sQ==@protonmail.internalid> <20260427-msm8939-venus-rfc-v3-7-288195bb7917@gmail.com> <0ee6bf23-17a3-4a7c-93d2-276e97cc3a14@kernel.org> <1120b76e-3c98-4f32-821f-baab667dfc38@oss.qualcomm.com> Content-Language: en-US From: Erikas Bitovtas In-Reply-To: <1120b76e-3c98-4f32-821f-baab667dfc38@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 4/29/26 12:18 PM, Konrad Dybcio wrote: > On 4/29/26 6:14 AM, Bryan O'Donoghue wrote: >> On 27/04/2026 18:58, Erikas Bitovtas wrote: >>> Since in downstream kernel VENUS_CORE0_GDSC and VENUS_CORE1_GDSC have a >>> device tree property "qcom,supports-hw-trigger", add a HW_CTRL flag >>> to these GDSCs to indicate that they are hardware controlled. >>> >>> Venus core clock cannot be enabled if Venus core GDSCs are switched off. >>> But since they are hardware controlled, they can be switched off at >>> any moment. Vote for the Venus core clock to enable it later when GDSCs >>> get turned on. >>> >>> Signed-off-by: Erikas Bitovtas >>> --- >>>   drivers/clk/qcom/gcc-msm8939.c | 4 ++++ >>>   1 file changed, 4 insertions(+) >>> >>> diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c >>> index 45193b3d714b..420997b00ae0 100644 >>> --- a/drivers/clk/qcom/gcc-msm8939.c >>> +++ b/drivers/clk/qcom/gcc-msm8939.c >>> @@ -3664,6 +3664,7 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { >>> >>>   static struct clk_branch gcc_venus0_core0_vcodec0_clk = { >>>       .halt_reg = 0x4c02c, >>> +    .halt_check = BRANCH_HALT_SKIP, >>>       .clkr = { >>>           .enable_reg = 0x4c02c, >>>           .enable_mask = BIT(0), >>> @@ -3681,6 +3682,7 @@ static struct clk_branch gcc_venus0_core0_vcodec0_clk = { >>> >>>   static struct clk_branch gcc_venus0_core1_vcodec0_clk = { >>>       .halt_reg = 0x4c034, >>> +    .halt_check = BRANCH_HALT_SKIP, >>>       .clkr = { >>>           .enable_reg = 0x4c034, >>>           .enable_mask = BIT(0), >>> @@ -3753,6 +3755,7 @@ static struct gdsc venus_core0_gdsc = { >>>       .pd = { >>>           .name = "venus_core0", >>>       }, >>> +    .flags = HW_CTRL, >>>       .pwrsts = PWRSTS_OFF_ON, >>>   }; >>> >>> @@ -3761,6 +3764,7 @@ static struct gdsc venus_core1_gdsc = { >>>       .pd = { >>>           .name = "venus_core1", >>>       }, >>> +    .flags = HW_CTRL, >>>       .pwrsts = PWRSTS_OFF_ON, >>>   }; >>> >>> >>> -- >>> 2.54.0 >>> >> >> The downstream opts to put the GDSC under hw control, which is not the same thing as it being under hw control, its up to you to put it under hw control. >> >> So you might want to be more conservative especially given you have a problem getting the encoder and decoder to run simultaneously - I might try parking this patch and then see what happens. > > i.e., Bryan is asking you to replace HW_CTRL with HW_CTRL_TRIGGER > I tried to revert the patch and replace HW_CTRL with HW_CTRL_TRIGGER - both result in power collapse fails.> Konrad