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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Linus Walleij <linusw@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	srinivas.kandagatla@oss.qualcomm.com
Subject: Re: [PATCH v1 1/3] pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM
Date: Tue, 14 Apr 2026 10:37:42 +0200	[thread overview]
Message-ID: <0975d136-0013-425b-a465-08f07efcefc7@oss.qualcomm.com> (raw)
In-Reply-To: <20260413122233.375945-2-ajay.nandam@oss.qualcomm.com>

On 4/13/26 2:22 PM, Ajay Kumar Nandam wrote:
> Convert the LPASS LPI pinctrl driver to use the PM clock framework for
> runtime power management.
> 
> This allows the LPASS LPI pinctrl driver to drop clock votes when idle,
> improves power efficiency on platforms using LPASS LPI island mode, and
> aligns the driver with common runtime PM patterns used across Qualcomm
> LPASS subsystems.
> 
> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
> ---
>  drivers/pinctrl/qcom/pinctrl-lpass-lpi.c      | 36 +++++++++++++------
>  drivers/pinctrl/qcom/pinctrl-lpass-lpi.h      |  2 ++
>  .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c   |  5 +++
>  3 files changed, 32 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> index 76aed3296..6d50e06ef 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -14,15 +14,16 @@
>  
>  #include <linux/pinctrl/pinconf-generic.h>
>  #include <linux/pinctrl/pinconf.h>
> +#include <linux/pm_runtime.h>
>  #include <linux/pinctrl/pinmux.h>
>  
>  #include "../pinctrl-utils.h"
>  
>  #include "pinctrl-lpass-lpi.h"
> +#include <linux/pm_clock.h>

Please move it up, together with other non-local includes

[...]

> +	pm_runtime_set_autosuspend_delay(dev, 100);
> +	pm_runtime_use_autosuspend(dev);
> +	pm_runtime_enable(dev);

devm_pm_runtime_enable() will let you drop the manual disablement below and
in .remove()

>  
>  	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
>  	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
> @@ -539,20 +540,33 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
>  	return 0;
>  
>  err_pinctrl:
> +	pm_runtime_disable(dev);
>  	mutex_destroy(&pctrl->lock);
> -	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
>  
>  	return ret;
>  }

[...]

> --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> @@ -139,10 +139,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>  
> +static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
> +	RUNTIME_PM_OPS(lpi_pinctrl_runtime_suspend, lpi_pinctrl_runtime_resume, NULL)
> +};
> +
>  static struct platform_driver lpi_pinctrl_driver = {
>  	.driver = {
>  		   .name = "qcom-sc7280-lpass-lpi-pinctrl",
>  		   .of_match_table = lpi_pinctrl_of_match,
> +		   .pm = pm_ptr(&lpi_pinctrl_pm_ops),

I believe SoCs other than kodiak also require this change to avoid
regressions.

Konrad

  parent reply	other threads:[~2026-04-14  8:37 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-13 12:22 [PATCH v1 0/3] pinctrl: qcom: lpass-lpi: PM clock framework cleanup and fixes Ajay Kumar Nandam
2026-04-13 12:22 ` [PATCH v1 1/3] pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM Ajay Kumar Nandam
2026-04-14  8:33   ` Konrad Dybcio
2026-04-20  8:51     ` Ajay Kumar Nandam
2026-04-14  8:37   ` Konrad Dybcio [this message]
2026-04-16 12:32     ` Ajay Kumar Nandam
2026-04-13 12:22 ` [PATCH v1 2/3] pinctrl: qcom: lpass-lpi: Fix GPIO register access helper return types Ajay Kumar Nandam
2026-04-14  8:39   ` Konrad Dybcio
2026-04-20  8:42     ` Ajay Kumar Nandam
2026-04-13 12:22 ` [PATCH v1 3/3] pinctrl: qcom: lpass-lpi: Resume clocks for GPIO access Ajay Kumar Nandam
2026-04-14  8:44   ` Konrad Dybcio
2026-04-20  8:45     ` Ajay Kumar Nandam

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