From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Abel Vesa <abel.vesa@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>,
Sibi Sankar <quic_sibis@quicinc.com>
Cc: Johan Hovold <johan@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: qcom: x1e80100: Fix PCIe 6a reg offsets and add MHI
Date: Tue, 4 Jun 2024 14:04:18 +0200 [thread overview]
Message-ID: <09e6dbe0-d748-4333-b05b-32e96f96a2f6@linaro.org> (raw)
In-Reply-To: <20240531-x1e80100-dts-fixes-pcie6a-v1-1-1573ebcae1e8@linaro.org>
On 5/31/24 19:00, Abel Vesa wrote:
> The actual size of the DBI region is 0xf20 and the start of the
> ELBI region is 0xf40, according to the documentation. So fix them.
> While at it, add the MHI region as well.
>
> Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
There's a lot going on... but I suppose the change reflects the commit
message and that I suppose reflects reality
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
next prev parent reply other threads:[~2024-06-04 12:04 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-31 17:00 [PATCH 0/2] arm64: dts: qcom: x1e80100: Fix the PCIe 6a node Abel Vesa
2024-05-31 17:00 ` [PATCH 1/2] arm64: dts: qcom: x1e80100: Fix PCIe 6a reg offsets and add MHI Abel Vesa
2024-06-04 12:04 ` Konrad Dybcio [this message]
2024-05-31 17:00 ` [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode Abel Vesa
2024-05-31 19:55 ` Dmitry Baryshkov
2024-06-03 12:52 ` Johan Hovold
2024-06-04 12:00 ` Konrad Dybcio
2024-06-04 12:20 ` Johan Hovold
2024-06-04 12:38 ` Konrad Dybcio
2024-06-04 12:45 ` Abel Vesa
2024-06-04 12:55 ` Konrad Dybcio
2024-06-04 14:35 ` Abel Vesa
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