Re: [PATCH v3 2/2] drm/msm/dp: add support of max dp link rate

[Kuogee Hsieh <quic_khsieh@quicinc.com>]

On 11/18/2022 3:04 AM, Dmitry Baryshkov wrote:
> On 18/11/2022 01:49, Kuogee Hsieh wrote:
>> dp_out endpoint contains both data-lanes and link-frequencies 
>> properties.
>> This patch parser dp_out endpoint properties and acquire dp_max_lanes 
>> and
>> dp_max_link_rate from respective property. Finally, comparing them 
>> against
>> both data lane and link rate read back from sink to ensure both data 
>> lane
>> and link rate are supported by platform.
>> In the case there is no data-lanes or link-frequencies property 
>> defined at
>> dp_out endpoint, the default value are 4 data lanes with 5.4 Ghz link 
>> rate.
>>
>> Changes in v2:
>> -- add max link rate from dtsi
>>
>> Changes in v3:
>> -- parser max_data_lanes and max_dp_link_rate from dp_out endpoint
>>
>> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi |  1 +
>
> Should not be a part of this patch.
>
>>   drivers/gpu/drm/msm/dp/dp_display.c  | 4 ++++
>>   drivers/gpu/drm/msm/dp/dp_panel.c    |  7 ++++---
>>   drivers/gpu/drm/msm/dp/dp_panel.h    |  1 +
>>   drivers/gpu/drm/msm/dp/dp_parser.c   | 30 
>> ++++++++++++++++++++++--------
>>   drivers/gpu/drm/msm/dp/dp_parser.h   |  2 ++
>>   6 files changed, 34 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 4afe53b..d456e76 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -3897,6 +3897,7 @@
>>                           reg = <0>;
>>                           dp_in: endpoint {
>>                               remote-endpoint = <&dpu_intf0_out>;
>> +                            data-lanes = <0 1 2 3>;
>>                           };
>>                       };
>>                   };
>> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
>> b/drivers/gpu/drm/msm/dp/dp_display.c
>> index 29c9845..4fe2092 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_display.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
>> @@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct 
>> dp_display_private *dp)
>>       struct edid *edid;
>>         dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
>> +    dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
>> +
>> +    drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
>> +        dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
>>         rc = dp_panel_read_sink_caps(dp->panel, 
>> dp->dp_display.connector);
>>       if (rc)
>> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c 
>> b/drivers/gpu/drm/msm/dp/dp_panel.c
>> index 5149ceb..933fa9c 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
>> @@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel 
>> *dp_panel)
>>       link_info->rate = 
>> drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
>>       link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & 
>> DP_MAX_LANE_COUNT_MASK;
>>   +    /* Limit data lanes from data-lanes of endpoint properity of 
>> dtsi */
>>       if (link_info->num_lanes > dp_panel->max_dp_lanes)
>>           link_info->num_lanes = dp_panel->max_dp_lanes;
>>   -    /* Limit support upto HBR2 until HBR3 support is added */
>> -    if (link_info->rate >= 
>> (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
>> -        link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
>> +    /* Limit link rate from link-frequencies of endpoint properity 
>> of dtsi */
>> +    if (link_info->rate > dp_panel->max_dp_link_rate)
>> +        link_info->rate = dp_panel->max_dp_link_rate;
>>         drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
>>       drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
>> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h 
>> b/drivers/gpu/drm/msm/dp/dp_panel.h
>> index d861197a..f04d021 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_panel.h
>> +++ b/drivers/gpu/drm/msm/dp/dp_panel.h
>> @@ -50,6 +50,7 @@ struct dp_panel {
>>         u32 vic;
>>       u32 max_dp_lanes;
>> +    u32 max_dp_link_rate;
>>         u32 max_bw_code;
>>   };
>> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c 
>> b/drivers/gpu/drm/msm/dp/dp_parser.c
>> index dd73221..667981e 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_parser.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_parser.c
>> @@ -94,16 +94,30 @@ static int dp_parser_ctrl_res(struct dp_parser 
>> *parser)
>>   static int dp_parser_misc(struct dp_parser *parser)
>>   {
>>       struct device_node *of_node = parser->pdev->dev.of_node;
>> -    int len;
>> -
>> -    len = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
>> -    if (len < 0) {
>> -        DRM_WARN("Invalid property \"data-lanes\", default max DP 
>> lanes = %d\n",
>> -             DP_MAX_NUM_DP_LANES);
>> -        len = DP_MAX_NUM_DP_LANES;
>> +    struct device_node *endpoint;
>> +    int cnt;
>> +    u32 frequence = 0;
>> +
>> +    endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0);
>> +
>> +    if (endpoint) {
>> +        cnt = of_property_count_u32_elems(endpoint, "data-lanes");
>> +        if (cnt < 0)
>> +            parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
>> +        else
>> +            parser->max_dp_lanes = cnt;
>
> This should be a separate patch. And now what, 
> drm_of_get_data_lanes_count() can be used here too. Why are you 
> dropping the generic function for the sake of your custom implementatoin.
drm_of_get_data_lanes_count() expect the parent node of endpoint.

It will locate endpoint first and call of_property_count_u32_elems() to 
retrieve count of elements and there is no similar function for 
link-frequencies.

To get link-frequencies we have to locate endpoint already. so why not 
use same endpoint for both data-lanes and link-frequencies.

So that consistent way are used  to retrieve both data-lanes and 
link-frequencies.




>
>> +
>> +        cnt = of_property_count_u32_elems(endpoint, 
>> "link-frequencies");
>> +        if (cnt < 0) {
>> +            parser->max_dp_link_rate = DP_LINK_FREQUENCY_HBR2; /* 
>> 54000 khz */
>> +        } else {
>> +            of_property_read_u32_array(endpoint, "link-frequencies", 
>> &frequence, 1);
>
> link-frequencies is u64 array.
>
>> +            parser->max_dp_link_rate = frequence;
>> +        }
>>       }
>>   -    parser->max_dp_lanes = len;
>> +    pr_err("%s: kuogee, lane=%d frequency=%d\n", __func__, 
>> parser->max_dp_lanes, parser->max_dp_link_rate);
>> +
>
> Leftover?
>
>>       return 0;
>>   }
>>   diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h 
>> b/drivers/gpu/drm/msm/dp/dp_parser.h
>> index 866c1a8..76ddb751 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_parser.h
>> +++ b/drivers/gpu/drm/msm/dp/dp_parser.h
>> @@ -15,6 +15,7 @@
>>   #define DP_LABEL "MDSS DP DISPLAY"
>>   #define DP_MAX_PIXEL_CLK_KHZ    675000
>>   #define DP_MAX_NUM_DP_LANES    4
>> +#define DP_LINK_FREQUENCY_HBR2    540000
>>     enum dp_pm_type {
>>       DP_CORE_PM,
>> @@ -119,6 +120,7 @@ struct dp_parser {
>>       struct dp_io io;
>>       struct dp_display_data disp_data;
>>       u32 max_dp_lanes;
>> +    u32 max_dp_link_rate;
>>       struct drm_bridge *next_bridge;
>>         int (*parse)(struct dp_parser *parser);
>