From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C5BD12010E3; Tue, 4 Mar 2025 12:28:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741091322; cv=none; b=AI7kaeoOZgCDAXSK1TO8kBMdJtfA/swJcsr4RilxMoM/HgijIVSFS3mwVnX4i9VVayirfDTAvCXShatT7Y+3fsVSk/gnFvGApmkYSAzLzxP1fgp5Bl73xcOVo2Oyyr63XejqImHdmjdlkKQYWifFJvkv17w2oZUNYj3+cmt6YO0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741091322; c=relaxed/simple; bh=7CVK5RriPNiuTywe/Ytj/4JBL8PgijKTyYnsve+78ps=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Yp1sozUlYMwbOx2jg1EdVbGJP2PL9lWI7UidI9kK8d1QZvd/wLkoBvy6lOWZKntebMNAKKoiSq8k6yormRrrgIpP7wTgdxX06tryJc03lc2ErIhIMd4TOgTboFiZsY84xTbQRFisqmsNHJkw/iMCf4euQoxERyjFF2u6ahyxcC4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4573BFEC; Tue, 4 Mar 2025 04:28:52 -0800 (PST) Received: from [10.1.197.1] (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 54D7C3F5A1; Tue, 4 Mar 2025 04:28:36 -0800 (PST) Message-ID: <0be31ecd-4386-4eb6-ad6f-a4409a3fc6ad@arm.com> Date: Tue, 4 Mar 2025 12:28:23 +0000 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v15 10/10] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes To: Jie Gan , Mike Leach , James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Konrad Dybcio References: <20250303032931.2500935-1-quic_jiegan@quicinc.com> <20250303032931.2500935-11-quic_jiegan@quicinc.com> Content-Language: en-US From: Suzuki K Poulose In-Reply-To: <20250303032931.2500935-11-quic_jiegan@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/03/2025 03:29, Jie Gan wrote: > Add CTCU and ETR nodes in DT to enable related functionalities. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Jie Gan Assuming this goes via the soc tree, Acked-by: Suzuki K Poulose > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++ > 1 file changed, 153 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 3394ae2d1300..31aa94d2a043 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -2429,6 +2429,35 @@ crypto: crypto@1dfa000 { > interconnect-names = "memory"; > }; > > + ctcu@4001000 { > + compatible = "qcom,sa8775p-ctcu"; > + reg = <0x0 0x04001000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + ctcu_in0: endpoint { > + remote-endpoint = <&etr0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + ctcu_in1: endpoint { > + remote-endpoint = <&etr1_out>; > + }; > + }; > + }; > + }; > + > stm: stm@4002000 { > compatible = "arm,coresight-stm", "arm,primecell"; > reg = <0x0 0x4002000 0x0 0x1000>, > @@ -2633,6 +2662,122 @@ qdss_funnel_in1: endpoint { > }; > }; > > + replicator@4046000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x0 0x04046000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + qdss_rep_in: endpoint { > + remote-endpoint = <&swao_rep_out0>; > + }; > + }; > + }; > + > + out-ports { > + port { > + qdss_rep_out0: endpoint { > + remote-endpoint = <&etr_rep_in>; > + }; > + }; > + }; > + }; > + > + tmc_etr: tmc@4048000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x0 0x04048000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + iommus = <&apps_smmu 0x04c0 0x00>; > + > + arm,scatter-gather; > + > + in-ports { > + port { > + etr0_in: endpoint { > + remote-endpoint = <&etr_rep_out0>; > + }; > + }; > + }; > + > + out-ports { > + port { > + etr0_out: endpoint { > + remote-endpoint = <&ctcu_in0>; > + }; > + }; > + }; > + }; > + > + replicator@404e000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x0 0x0404e000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + etr_rep_in: endpoint { > + remote-endpoint = <&qdss_rep_out0>; > + }; > + }; > + }; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + etr_rep_out0: endpoint { > + remote-endpoint = <&etr0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + etr_rep_out1: endpoint { > + remote-endpoint = <&etr1_in>; > + }; > + }; > + }; > + }; > + > + tmc_etr1: tmc@404f000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x0 0x0404f000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + iommus = <&apps_smmu 0x04a0 0x40>; > + > + arm,scatter-gather; > + arm,buffer-size = <0x400000>; > + > + in-ports { > + port { > + etr1_in: endpoint { > + remote-endpoint = <&etr_rep_out1>; > + }; > + }; > + }; > + > + out-ports { > + port { > + etr1_out: endpoint { > + remote-endpoint = <&ctcu_in1>; > + }; > + }; > + }; > + }; > + > funnel@4b04000 { > compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > reg = <0x0 0x4b04000 0x0 0x1000>; > @@ -2708,6 +2853,14 @@ out-ports { > #address-cells = <1>; > #size-cells = <0>; > > + port@0 { > + reg = <0>; > + > + swao_rep_out0: endpoint { > + remote-endpoint = <&qdss_rep_in>; > + }; > + }; > + > port@1 { > reg = <1>; > swao_rep_out1: endpoint {