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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDE3OSBTYWx0ZWRfX72lPX1CGeZxi kdtHjM91BNiVAjG4uO5rudr1GS+o3fWdf9lLES8E1+5kn7sureZ85zUXOKf0xfXEtnGLzdt+MWy 7GmebAfxY6dp2PH6gkzowoK5HXFRTOJIfO9fXWRdvxfOYNNrktEfe99pv6NOS+Ar9ficfXuYumc MZGLjp4+DiVj77AHY3+HiPi6QlYYWD5GEY0kytXNwZ0mu06JZH0oETRORUomTWNIPJJnUF+z9hp T/DS89Oh7pukZGzuH95HLT0+fJRPOk07p5+UDPNKlny2pprc578oQvVDtqyolroCvFVf2Kjb4Ke jl60zYr/EpyvjEhsM1jGlCBX+GuTs4ly67oQvrHnCPH63/+SLiSGg+vGERikm3tTyKZKtuIMX9y pAk4E+rnhaE5sg4wvpH2BlGAMfFBj4zyocHmZhZ667YrbP6V0GFf5KDrfU8KmmIFhRfv3JNqgFv bkkS3lKlC7cAEJn7+IQ== X-Proofpoint-GUID: TCvNQCPZDbGGPtVppvaVLPt6R0oXz0YT X-Proofpoint-ORIG-GUID: TCvNQCPZDbGGPtVppvaVLPt6R0oXz0YT X-Authority-Analysis: v=2.4 cv=T/eBjvKQ c=1 sm=1 tr=0 ts=69499dc3 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=oy5nMm26i85I/VS19bmskg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=dk0i7xQ4PQfej7aG6gsA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-22_03,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220179 On 12/21/2025 10:15 PM, Johan Hovold wrote: > The hw clock gating register sequence consists of register value pairs > that are written to the GPU during initialisation. > > The a690 hwcg sequence has two GMU registers in it that used to amount > to random writes in the GPU mapping, but since commit 188db3d7fe66 > ("drm/msm/a6xx: Rebase GMU register offsets") they trigger a fault as > the updated offsets now lie outside the mapping. This in turn breaks > boot of machines like the Lenovo ThinkPad X13s. > > Note that the updates of these GMU registers is already taken care of > properly since commit 40c297eb245b ("drm/msm/a6xx: Set GMU CGC > properties on a6xx too"), but for some reason these two entries were > left in the table. > > Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support") > Cc: stable@vger.kernel.org # 6.5 > Cc: Bjorn Andersson > Cc: Konrad Dybcio > Signed-off-by: Johan Hovold Reviewed-by: Akhil P Oommen I fixed a similar out of bound access issue in the coredump path last month. This pattern indicates that we should consider combining the IO accessors of both gpu and gmu. -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 29107b362346..4c2f739ee9b7 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -501,8 +501,6 @@ static const struct adreno_reglist a690_hwcg[] = { > {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, > {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, > {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, > - {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, > - {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, > {} > }; >