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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b842a511551sm486275966b.53.2026.01.07.04.16.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Jan 2026 04:16:48 -0800 (PST) Message-ID: <0ff8041a-c876-419e-8f18-7656e29549a3@oss.qualcomm.com> Date: Wed, 7 Jan 2026 13:16:46 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] clk: qcom: cmnpll: Account for reference clock divider To: Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Luo Jie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com References: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com> <20260106-qcom_ipq5332_cmnpll-v2-1-f9f7e4efbd79@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260106-qcom_ipq5332_cmnpll-v2-1-f9f7e4efbd79@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDA5NSBTYWx0ZWRfXz7NAMqMB0BWa O8KkbGpkhHrQ6rK/YrX8TRnKNoEJKdVQw9eKdvG/0GC8pKegOrlzK0CJPx/7U5NAuGJ83+KlgeY gCIu7sJOQJlXRlFnMmPHTF6N6ZavinElrXq6vYce/tNFezZpcQ6GIjuF+imBWu5oC5hCY8DjS7A RSg8s3u/sWC0YX0i2RoVPRgoO6ZAs3cdYyndWmhT6rfYJl+V6drUed0ZaDpY3oqrXORBd7vHzBz pxr7S5o60z+NZTBUWj7YmGGyYiBkFcqEOEoZyyCLmq/QP464VqdxUStj+jJumaNWqiCMuR2K8P3 fGPf0qb5vvFJdDNeMzoHofEfO/uzaRYELoHWIzJ/KHjVG/vgTmMxVV6ztl/J0ymCSzVzHMTA7CO MYwHoMBxVCs3zrV8q9eOqJiehZWiBQvDf8SDJmICafvsUPUlW12T0+vQ9GIEcqa3L95JV4S0mOv TTCyJC1XN1BncbcunTg== X-Proofpoint-GUID: yRA8En138xVM1gsce7lZ27MO5_nTy34j X-Proofpoint-ORIG-GUID: yRA8En138xVM1gsce7lZ27MO5_nTy34j X-Authority-Analysis: v=2.4 cv=Abi83nXG c=1 sm=1 tr=0 ts=695e4eb2 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=QfgEeMFAfvcTqVishicA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-07_01,2026-01-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601070095 On 1/7/26 6:35 AM, Luo Jie wrote: > The clk_cmn_pll_recalc_rate() function must account for the reference clock > divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms > with a reference divider other than 1 calculate incorrect CMN PLL rates. > For example, on IPQ5332 where the reference divider is 2, the computed rate > becomes twice the actual output. > > Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before > applying the 2 * FACTOR scaling. This yields the correct rate calculation: > rate = (parent_rate / ref_div) * 2 * factor. > > Maintain backward compatibility with earlier platforms (e.g. IPQ9574, > IPQ5424, IPQ5018) that use ref_div = 1. > > Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC") > Signed-off-by: Luo Jie > --- > drivers/clk/qcom/ipq-cmn-pll.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c > index dafbf5732048..369798d1ce42 100644 > --- a/drivers/clk/qcom/ipq-cmn-pll.c > +++ b/drivers/clk/qcom/ipq-cmn-pll.c > @@ -185,7 +185,7 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, > unsigned long parent_rate) > { > struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); > - u32 val, factor; > + u32 val, factor, ref_div; > > /* > * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted > @@ -193,8 +193,15 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, > */ > regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); > factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); > + if (WARN_ON(factor == 0)) > + factor = 1; FWIW the docs tell me the value of this field is '192' on IPQ5332.. Konrad