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Mon, 25 Nov 2024 01:44:23 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AP1iMhU025369 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 01:44:22 GMT Received: from [10.64.16.151] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 24 Nov 2024 17:44:15 -0800 Message-ID: <10413094-500f-4044-b4e3-8ce83fee3dbd@quicinc.com> Date: Mon, 25 Nov 2024 09:44:12 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support To: Dmitry Baryshkov CC: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Krishna Manikandan" , Bjorn Andersson , Konrad Dybcio , "Catalin Marinas" , Will Deacon , Li Liu , Xiangxu Yin , , , , , , References: <20241122-add-display-support-for-qcs615-platform-v3-0-35252e3a51fe@quicinc.com> <20241122-add-display-support-for-qcs615-platform-v3-5-35252e3a51fe@quicinc.com> Content-Language: en-US From: fange zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ALnY4WQC7U_GidKZVMBIyRRX_D5Sz7vY X-Proofpoint-ORIG-GUID: ALnY4WQC7U_GidKZVMBIyRRX_D5Sz7vY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250013 On 2024/11/22 18:07, Dmitry Baryshkov wrote: > On Fri, Nov 22, 2024 at 05:56:48PM +0800, Fange Zhang wrote: >> From: Li Liu >> >> Add definitions for the display hardware used on the Qualcomm SM6150 >> platform. >> >> Signed-off-by: Li Liu >> Signed-off-by: Fange Zhang >> --- >> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + >> 4 files changed, 266 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h >> new file mode 100644 >> index 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75 >> --- /dev/null >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h >> @@ -0,0 +1,263 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> +/* >> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#ifndef _DPU_5_3_SM6150_H >> +#define _DPU_5_3_SM6150_H >> + >> + }, { >> + .name = "intf_2", .id = INTF_2, >> + .base = 0x6b000, .len = 0x2c0, >> + .features = INTF_SC7180_MASK, >> + .type = INTF_NONE, >> + .controller_id = 0, >> + .prog_fetch_lines_worst_case = 24, >> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), >> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), > > Please drop. No need to declare missing blocks. got it, will remove this block in the next patch > > Other than that: > > Reviewed-by: Dmitry Baryshkov > > >> + }, { >> + .name = "intf_3", .id = INTF_3, >> + .base = 0x6b800, .len = 0x280, >> + .features = INTF_SC7180_MASK, >> + .type = INTF_DP, >> + .controller_id = MSM_DP_CONTROLLER_1, >> + .prog_fetch_lines_worst_case = 24, >> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), >> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), >> + }, >> +}; >> + >