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[83.9.31.20]) by smtp.gmail.com with ESMTPSA id 21-20020a170906311500b0087045ae5935sm9813939ejx.1.2023.02.01.02.40.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Feb 2023 02:40:34 -0800 (PST) Message-ID: <11859977-4e29-e4d7-acd4-94e3d3227c27@linaro.org> Date: Wed, 1 Feb 2023 11:40:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v2] arm64: Add a couple of missing part numbers To: Anshuman Khandual , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Catalin Marinas , Will Deacon , Marc Zyngier , James Morse , D Scott Phillips , Michal Orzel , Linu Cherian , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230201000900.3150295-1-konrad.dybcio@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 1.02.2023 05:50, Anshuman Khandual wrote: > > > On 2/1/23 05:39, Konrad Dybcio wrote: >> Add Cortex X1C and add/clarify various recent Qualcomm Kryo cores, >> which almost exclusively mimic ARM IDs nowadays. > > Why add these cpu numbers ? Is there an errata being worked on for them ? > Without specific implementation requirement, these might not be necessary. Generally I was under the impression that this header double-served as sort of a documentation. I checked my board and they seem to even use the Arm implementer ID (instead of their own, as they did in the past), so I suppose they may be using actual Cortex parts with no modifications and this patch is not very beneficial. Konrad > >> >> Signed-off-by: Konrad Dybcio >> --- >> v1 -> v2: >> >> - Don't change the name of QCOM_CPU_PART_KRYO_4XX_SILVER >> >> arch/arm64/include/asm/cputype.h | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h >> index 683ca3af4084..a4260d3194fc 100644 >> --- a/arch/arm64/include/asm/cputype.h >> +++ b/arch/arm64/include/asm/cputype.h >> @@ -84,6 +84,7 @@ >> #define ARM_CPU_PART_CORTEX_X2 0xD48 >> #define ARM_CPU_PART_NEOVERSE_N2 0xD49 >> #define ARM_CPU_PART_CORTEX_A78C 0xD4B >> +#define ARM_CPU_PART_CORTEX_X1C 0xD4C >> >> #define APM_CPU_PART_POTENZA 0x000 >> >> @@ -107,9 +108,17 @@ >> #define QCOM_CPU_PART_KRYO 0x200 >> #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 >> #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 >> +#define QCOM_CPU_PART_KRYO_3XX_GOLD 0x802 >> #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 >> #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 >> #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 >> +#define QCOM_CPU_PART_KRYO_5XX_GOLD ARM_CPU_PART_CORTEX_A77 >> +#define QCOM_CPU_PART_KRYO_6XX_GOLD ARM_CPU_PART_CORTEX_A78 >> +#define QCOM_CPU_PART_KRYO_6XX_GOLDPLUS ARM_CPU_PART_CORTEX_X1 >> +#define QCOM_CPU_PART_KRYO_6XX_SILVER_V1 ARM_CPU_PART_CORTEX_A55 >> +#define QCOM_CPU_PART_KRYO_7XX_GOLD ARM_CPU_PART_CORTEX_A710 >> +#define QCOM_CPU_PART_KRYO_7XX_GOLDPLUS ARM_CPU_PART_CORTEX_X2 >> +#define QCOM_CPU_PART_KRYO_7XX_SILVER ARM_CPU_PART_CORTEX_A510 >> >> #define NVIDIA_CPU_PART_DENVER 0x003 >> #define NVIDIA_CPU_PART_CARMEL 0x004