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Thu, 19 Feb 2026 06:46:31 -0800 (PST) X-Received: by 2002:a17:90b:530c:b0:340:25f0:a9b with SMTP id 98e67ed59e1d1-358450eca59mr17324750a91.33.1771512391299; Thu, 19 Feb 2026 06:46:31 -0800 (PST) Received: from [192.168.1.6] ([49.204.108.219]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35894b32cbesm1520691a91.0.2026.02.19.06.46.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Feb 2026 06:46:30 -0800 (PST) Message-ID: <12063990-70fe-4faf-89fa-c74c7bd97f42@oss.qualcomm.com> Date: Thu, 19 Feb 2026 20:16:21 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 13/13] i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms To: Konrad Dybcio , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mukesh Kumar Savaliya , Viken Dadhaniya , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: prasad.sodagudi@oss.qualcomm.com, quic_vtanuku@quicinc.com, aniket.randive@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, jyothi.seerapu@oss.qualcomm.com, chiluka.harish@oss.qualcomm.com References: <20260206174112.4149893-1-praveen.talari@oss.qualcomm.com> <20260206174112.4149893-14-praveen.talari@oss.qualcomm.com> <389dc762-bd20-44e5-a3fc-256b42f3c82a@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: <389dc762-bd20-44e5-a3fc-256b42f3c82a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ieBExlfLhNwVk8B5zCicBcZdHfAj6F-4 X-Proofpoint-ORIG-GUID: ieBExlfLhNwVk8B5zCicBcZdHfAj6F-4 X-Authority-Analysis: v=2.4 cv=A6hh/qWG c=1 sm=1 tr=0 ts=69972248 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=SEi2w9hYDuVaAARFuk79KQ==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=0Va3wKG2juJEggPPLkUA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDEzNSBTYWx0ZWRfXyfTp7lBVDQ32 wctGRAUbDfQ9dhRpEAVQCtl3Q8ViFK3f+aR0n4A8rsgW+NiBM42OTpPtEosZuSWwONMXX4WM2O4 iQhdO8hBEtK3GFhJ2DjAvVSbCXb5HwuIPaCW82/ysJW2EdqxZC3pab3SoawM7vpBa/0KMO274S/ 4rva79jcOb/lwOwz97TdOOVa5tsppOeaPi88gOxXU9mZ/kCIMKMj9NFQfeYk9zX/8NrlsM9w8Hf 00jaMbqSYDWbWOeZ9InDN5vP0Z7wC1EgZUsPksCL9Kne7amIR5DtZL3nlYiSywmtNG3MN/WSti1 K2dhxJBWqxPZVAO2uhGkZ8ia+OaovAKYP2CBIyGXJVlRP8+JlU+U5XAUe1W80OliKO0IW6E4o6T kXgmEiA8/bW1jZoY+S6pDbf6t1U+VIolmFRH5Oj4d0F36MsEF/IaByvLSFexJeEYLdlu87eatsO 65GCZjXEuidcRhCjWzg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_04,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602190135 Hi On 2/17/2026 5:20 PM, Konrad Dybcio wrote: > On 2/6/26 6:41 PM, Praveen Talari wrote: >> The Qualcomm automotive SA8255p SoC relies on firmware to configure >> platform resources, including clocks, interconnects and TLMM. >> The driver requests resources operations over SCMI using power >> and performance protocols. >> >> The SCMI power protocol enables or disables resources like clocks, >> interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, >> such as resume/suspend, to control power on/off. >> >> The SCMI performance protocol manages I2C frequency, with each >> frequency rate represented by a performance level. The driver uses >> geni_se_set_perf_opp() API to request the desired frequency rate.. >> >> As part of geni_se_set_perf_opp(), the OPP for the requested frequency >> is obtained using dev_pm_opp_find_freq_floor() and the performance >> level is set using dev_pm_opp_set_opp(). >> >> Acked-by: Viken Dadhaniya >> Signed-off-by: Praveen Talari >> --- > > [...] > >> @@ -215,6 +220,7 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) >> val |= itr->t_low_cnt << LOW_COUNTER_SHFT; >> val |= itr->t_cycle_cnt; >> writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); >> + return 0; > > ultra nit: a \n before return statements is preferred Sure, will do it in next patch > > [...] > >> static const struct geni_i2c_desc i2c_master_hub = { >> .no_dma_support = true, >> .tx_fifo_depth = 16, >> + .resources_init = geni_i2c_resources_init, >> + .set_rate = qcom_geni_i2c_conf, >> + .power_on = geni_se_resources_activate, >> + .power_off = geni_se_resources_deactivate, >> +}; >> + >> +static const struct geni_i2c_desc sa8255p_geni_i2c = { >> + .resources_init = geni_se_domain_attach, >> + .set_rate = geni_se_set_perf_opp, > > I noticed that because this lacks .power_on/off, the > pinctrl_pm_select_xxx_state() functions are never called. Are the GPIOs > managed through the power/perf domains of the QUP devices too? (I would Yes, GPIOs are managed by Firmware, not by Linux. > assume not since there's a TLMM node in [0]) I don't know the exact reason for this node in DT. Thanks, Praveen Talari > > Konrad > > [0] https://lore.kernel.org/linux-arm-msm/20250422231249.871995-1-quic_djaggi@quicinc.com/