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Mon, 3 Oct 2022 19:40:14 GMT Received: from [10.110.93.213] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 3 Oct 2022 12:40:12 -0700 Message-ID: <12e69213-c09d-fe48-8fa3-022a3e6f76cc@quicinc.com> Date: Mon, 3 Oct 2022 14:40:11 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH 4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks Content-Language: en-US To: Dmitry Baryshkov CC: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , Marc Zyngier , , , , References: <20221001030403.27659-1-quic_molvera@quicinc.com> <20221001030403.27659-5-quic_molvera@quicinc.com> From: Melody Olvera In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cvmEuxHGarCPFeMc0rWH_adGrBGBgcFn X-Proofpoint-ORIG-GUID: cvmEuxHGarCPFeMc0rWH_adGrBGBgcFn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-03_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210030118 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 10/1/2022 2:03 AM, Dmitry Baryshkov wrote: > On Sat, 1 Oct 2022 at 06:05, Melody Olvera wrote: >> Add support for RMPh clocks for QDU1000 and QRU1000 SoCs. >> >> Signed-off-by: Melody Olvera >> --- >> drivers/clk/qcom/clk-rpmh.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c >> index c07cab6905cb..27d11ffac71e 100644 >> --- a/drivers/clk/qcom/clk-rpmh.c >> +++ b/drivers/clk/qcom/clk-rpmh.c >> @@ -628,6 +628,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = { >> .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), >> }; >> >> +DEFINE_CLK_RPMH_ARC(qdru1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); >> + >> +static struct clk_hw *qdru1000_rpmh_clocks[] = { >> + [RPMH_CXO_CLK] = &qdru1000_bi_tcxo.hw, >> + [RPMH_CXO_CLK_A] = &qdru1000_bi_tcxo_ao.hw, >> +}; >> + >> +static const struct clk_rpmh_desc clk_rpmh_qdru1000 = { >> + .clks = qdru1000_rpmh_clocks, >> + .num_clks = ARRAY_SIZE(qdru1000_rpmh_clocks), >> +}; >> + >> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, >> void *data) >> { >> @@ -723,6 +735,8 @@ static const struct of_device_id clk_rpmh_match_table[] = { >> { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, >> { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, >> { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, >> + { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdru1000}, >> + { .compatible = "qcom,qru1000-rpmh-clk", .data = &clk_rpmh_qdru1000}, > Also the list isn't fully sorted, let's target that. Please move your > compat strings into the beginning. Sure thing. > >> { } >> }; >> MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); >> -- >> 2.37.3 >> Thanks, Melody