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> }; > > +enum dll_init_context { > + DLL_INIT_NORMAL, > + DLL_INIT_FROM_CX_COLLAPSE_EXIT, DLL_INIT_FROM_CX_COLLAPSE_EXIT is never used? > +}; > + > +enum mode { > + HS400, // equivalent to SDR104 mode for DLL. > + HS200, // equivalent to SDR50 mode for DLL. > +}; > + > static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host) > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > @@ -803,6 +815,209 @@ static int msm_init_cm_dll(struct sdhci_host *host) > return 0; > } > > +static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) > +{ > + return SDHCI_MSM_MIN_CLOCK; > +} > + > +static unsigned int sdhci_msm_get_clk_rate(struct sdhci_host *host, u32 req_clk) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + struct clk *core_clk = msm_host->bulk_clks[0].clk; > + struct mmc_ios ios = host->mmc->ios; > + unsigned int sup_clk; > + > + if (req_clk < sdhci_msm_get_min_clock(host)) > + return sdhci_msm_get_min_clock(host); > + > + sup_clk = clk_get_rate(core_clk); > + > + if (ios.timing == MMC_TIMING_MMC_HS400 || > + host->flags & SDHCI_HS400_TUNING) > + sup_clk = sup_clk / 2; > + > + return sup_clk; > +} > + > +/* Initialize the DLL (Programmable Delay Line) */ > +static int sdhci_msm_configure_dll(struct sdhci_host *host, enum dll_init_context > + init_context, enum mode index) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + const struct sdhci_msm_offset *msm_offset = msm_host->offset; > + struct mmc_host *mmc = host->mmc; > + u32 ddr_cfg_offset, core_vendor_spec, config; > + void __iomem *ioaddr = host->ioaddr; > + unsigned long flags, dll_clock; > + int rc = 0, wait_cnt = 50; > + > + dll_clock = sdhci_msm_get_clk_rate(host, host->clock); > + spin_lock_irqsave(&host->lock, flags); > + > + core_vendor_spec = readl_relaxed(ioaddr + msm_offset->core_vendor_spec); > + > + /* > + * Always disable PWRSAVE during the DLL power > + * up regardless of its current setting. > + */ > + core_vendor_spec &= ~CORE_CLK_PWRSAVE; > + writel_relaxed(core_vendor_spec, ioaddr + msm_offset->core_vendor_spec); > + > + if (msm_host->use_14lpp_dll_reset) { > + /* Disable CK_OUT */ > + config = readl_relaxed(ioaddr + msm_offset->core_dll_config); > + config &= ~CORE_CK_OUT_EN; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* Disable the DLL clock */ > + config = readl_relaxed(ioaddr + msm_offset->core_dll_config_2); > + config |= CORE_DLL_CLOCK_DISABLE; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); > + } > + > + /* > + * Write 1 to DLL_RST bit of DLL_CONFIG register > + * and Write 1 to DLL_PDN bit of DLL_CONFIG register. > + */ > + config = readl_relaxed(ioaddr + msm_offset->core_dll_config); > + config |= (CORE_DLL_RST | CORE_DLL_PDN); > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* > + * Configure DLL_CONFIG_3 and USER_CTRL > + * (Only applicable for 7FF projects). > + */ > + if (msm_host->core_minor >= SDHCI_MSM_MIN_V_7FF) { > + writel_relaxed(msm_host->dll[index].dll_config_3, > + ioaddr + msm_offset->core_dll_config_3); > + writel_relaxed(msm_host->dll[index].dll_usr_ctl, > + ioaddr + msm_offset->core_dll_usr_ctl); > + } > + > + /* > + * Set DDR_CONFIG since step 7 is setting TEST_CTRL that can be skipped. > + */ > + ddr_cfg_offset = msm_host->updated_ddr_cfg ? msm_offset->core_ddr_config > + : msm_offset->core_ddr_config_old; > + > + config = msm_host->dll[index].ddr_config; > + writel_relaxed(config, ioaddr + ddr_cfg_offset); > + > + /* Set DLL_CONFIG_2 */ > + if (msm_host->use_14lpp_dll_reset) { > + u32 mclk_freq; > + int cycle_cnt; > + > + /* > + * Only configure the mclk_freq in normal DLL init > + * context. If the DLL init is coming from > + * CX Collapse Exit context, the host->clock may be zero. > + * The DLL_CONFIG_2 register has already been restored to > + * proper value prior to getting here. > + */ > + if (init_context == DLL_INIT_NORMAL) { > + cycle_cnt = readl_relaxed(ioaddr + > + msm_offset->core_dll_config_2) > + & CORE_FLL_CYCLE_CNT ? 8 : 4; > + > + mclk_freq = DIV_ROUND_CLOSEST_ULL(dll_clock * cycle_cnt, TCXO_FREQ); > + > + if (dll_clock < 100000000) { > + pr_err("%s: %s: Non standard clk freq =%u\n", > + mmc_hostname(mmc), __func__, dll_clock); > + rc = -EINVAL; > + goto out; > + } > + > + config = readl_relaxed(ioaddr + msm_offset->core_dll_config_2); > + config = (config & ~GENMASK(17, 10)) | > + FIELD_PREP(GENMASK(17, 10), mclk_freq); > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); > + } > + /* wait for 5us before enabling DLL clock */ > + udelay(5); > + } > + > + config = msm_host->dll[index].dll_config; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* Wait for 52us */ > + spin_unlock_irqrestore(&host->lock, flags); > + usleep_range(60, 70); > + spin_lock_irqsave(&host->lock, flags); > + > + /* > + * Write 0 to DLL_RST bit of DLL_CONFIG register > + * and Write 0 to DLL_PDN bit of DLL_CONFIG register. > + */ > + config &= ~CORE_DLL_RST; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + config &= ~CORE_DLL_PDN; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + /* Write 1 to DLL_RST bit of DLL_CONFIG register */ > + config |= CORE_DLL_RST; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* Write 0 to DLL_RST bit of DLL_CONFIG register */ > + config &= ~CORE_DLL_RST; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* Set CORE_DLL_CLOCK_DISABLE to 0 */ > + if (msm_host->use_14lpp_dll_reset) { > + config = readl_relaxed(ioaddr + msm_offset->core_dll_config_2); > + config &= ~CORE_DLL_CLOCK_DISABLE; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); > + } > + > + /* Set DLL_EN bit to 1. */ > + config = readl_relaxed(ioaddr + msm_offset->core_dll_config); > + config |= CORE_DLL_EN; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* > + * Wait for 8000 input clock. Here we calculate the > + * delay from fixed clock freq 192MHz, which turns out 42us. > + */ > + spin_unlock_irqrestore(&host->lock, flags); > + usleep_range(50, 60); > + spin_lock_irqsave(&host->lock, flags); > + > + /* Set CK_OUT_EN bit to 1. */ > + config |= CORE_CK_OUT_EN; > + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); > + > + /* > + * Wait until DLL_LOCK bit of DLL_STATUS register > + * becomes '1'. > + */ > + while (!(readl_relaxed(ioaddr + msm_offset->core_dll_status) & > + CORE_DLL_LOCK)) { > + /* max. wait for 50us sec for LOCK bit to be set */ > + if (--wait_cnt == 0) { > + dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", > + mmc_hostname(mmc)); > + rc = -ETIMEDOUT; > + goto out; > + } > + /* wait for 1us before polling again */ > + udelay(1); > + } Please use an iopoll macro like readl_relaxed_poll_timeout_atomic(). > + > +out: > + if (core_vendor_spec & CORE_CLK_PWRSAVE) { > + /* Reenable PWRSAVE as needed */ > + config = readl_relaxed(ioaddr + msm_offset->core_vendor_spec); > + config |= CORE_CLK_PWRSAVE; > + writel_relaxed(config, ioaddr + msm_offset->core_vendor_spec); > + } > + > + spin_unlock_irqrestore(&host->lock, flags); > + return rc; > +} > + > static void msm_hc_select_default(struct sdhci_host *host) > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > @@ -925,14 +1140,31 @@ static void sdhci_msm_hc_select_mode(struct sdhci_host *host) > msm_hc_select_default(host); > } > > +static int sdhci_msm_init_dll(struct sdhci_host *host, enum dll_init_context init_context) > +{ > + if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 || > + host->mmc->ios.timing == MMC_TIMING_MMC_HS400) > + return sdhci_msm_configure_dll(host, init_context, HS400); > + > + return sdhci_msm_configure_dll(host, init_context, HS200); > +} > + > +static int sdhci_msm_dll_config(struct sdhci_host *host, enum dll_init_context init_context) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + > + return msm_host->artanis_dll ? sdhci_msm_init_dll(host, init_context) : > + msm_init_cm_dll(host); > +} > + > static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + const struct sdhci_msm_offset *msm_offset = msm_host->offset; > u32 config, calib_done; > int ret; > - const struct sdhci_msm_offset *msm_offset = > - msm_host->offset; > > pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); > > @@ -940,7 +1172,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) > * Retuning in HS400 (DDR mode) will fail, just reset the > * tuning block and restore the saved tuning phase. > */ > - ret = msm_init_cm_dll(host); > + ret = sdhci_msm_dll_config(host, DLL_INIT_NORMAL); > if (ret) > goto out; > > @@ -1028,7 +1260,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) > return ret; > } > > -static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) > +static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host, enum mode index) > { > struct mmc_host *mmc = host->mmc; > u32 dll_status, config, ddr_cfg_offset; > @@ -1051,7 +1283,11 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) > ddr_cfg_offset = msm_offset->core_ddr_config; > else > ddr_cfg_offset = msm_offset->core_ddr_config_old; > - writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); > + > + if (msm_host->artanis_dll) > + writel_relaxed(msm_host->dll[index].ddr_config, host->ioaddr + ddr_cfg_offset); > + else > + writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); > > if (mmc->ios.enhanced_strobe) { > config = readl_relaxed(host->ioaddr + > @@ -1108,11 +1344,10 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + const struct sdhci_msm_offset *msm_offset = msm_host->offset; > struct mmc_host *mmc = host->mmc; > - int ret; > u32 config; > - const struct sdhci_msm_offset *msm_offset = > - msm_host->offset; > + int ret; Here and elsewhere, this re-ordering of local definitions is a nice improvement but it would be better as a separate patch > > pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); > > @@ -1120,7 +1355,8 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) > * Retuning in HS400 (DDR mode) will fail, just reset the > * tuning block and restore the saved tuning phase. > */ > - ret = msm_init_cm_dll(host); > + ret = sdhci_msm_dll_config(host, DLL_INIT_NORMAL); > + > if (ret) > goto out; > > @@ -1140,7 +1376,7 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) > if (msm_host->use_cdclp533) > ret = sdhci_msm_cdclp533_calibration(host); > else > - ret = sdhci_msm_cm_dll_sdc4_calibration(host); > + ret = sdhci_msm_cm_dll_sdc4_calibration(host, HS400); > out: > pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), > __func__, ret); > @@ -1183,7 +1419,8 @@ static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host) > return 0; > > /* Reset the tuning block */ > - ret = msm_init_cm_dll(host); > + ret = sdhci_msm_dll_config(host, DLL_INIT_NORMAL); > + > if (ret) > return ret; > > @@ -1257,12 +1494,11 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) > if (host->flags & SDHCI_HS400_TUNING) { > sdhci_msm_hc_select_mode(host); > msm_set_clock_rate_for_bus_mode(host, ios.clock); > - host->flags &= ~SDHCI_HS400_TUNING; > } > > retry: > /* First of all reset the tuning block */ > - rc = msm_init_cm_dll(host); > + rc = sdhci_msm_dll_config(host, DLL_INIT_NORMAL); > if (rc) > return rc; > > @@ -1325,6 +1561,9 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) > rc = -EIO; > } > > + if (host->flags & SDHCI_HS400_TUNING) > + host->flags &= ~SDHCI_HS400_TUNING; Really the flag should be cleared on all return paths > + > if (!rc) > msm_host->tuning_done = true; > return rc; > @@ -1845,11 +2084,6 @@ static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) > return clk_round_rate(core_clk, ULONG_MAX); > } > > -static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) > -{ > - return SDHCI_MSM_MIN_CLOCK; > -} > - > /* > * __sdhci_msm_set_clock - sdhci_msm clock control. > *