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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2349325e16sm6094190a12.1.2025.05.12.11.33.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 May 2025 11:33:20 -0700 (PDT) Message-ID: <1347c6de-1748-4e35-a0ac-4fd77199045b@oss.qualcomm.com> Date: Mon, 12 May 2025 12:33:18 -0600 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] bus: mhi: host: Allocate entire MHI control config once To: Baochen Qiang , Manivannan Sadhasivam Cc: quic_carlv@quicinc.com, quic_thanson@quicinc.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, Pranjal Ramajor Asha Kanojiya References: <20250328165913.3380933-1-jeff.hugo@oss.qualcomm.com> <07cc4ee2-4a13-495c-bc4d-8837d6b54414@oss.qualcomm.com> <3d162e4f-a15f-4943-8639-ac8c47a77b93@quicinc.com> <723cb707-2bc2-481c-ab6a-1146c9677821@oss.qualcomm.com> <9ac836c0-2c41-4656-b922-5dc20aecf53f@quicinc.com> Content-Language: en-US From: Jeff Hugo In-Reply-To: <9ac836c0-2c41-4656-b922-5dc20aecf53f@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTEyMDE5MSBTYWx0ZWRfX68xzNS2URdsc kwbHxaz++HHT41dz/M9S6WfLQYMA30AIA0CXeWvoBxZtcYjmpXkjGe4pXxNLz39/L+U0RcV5frm ePEN9xZi/snD6BuSjzUMcnA6xLdhb2YYdbLGH8nkE002sOL6utuudFzfZyOjTJnVzMrqLlBCsXE l7GfHUH/u7XGOb0lCsbdlo80TskCI5EstkrCFcxrAQ0C8qSqKC+wxNlY8m7htDV8TrIBpy+iPFR DSbGLY37bWu/P8cW+akEIg76SWdlGEztfES3aU6RsVIqDVMSQdQl7V30zvwwPvPK5wsJq/11lJr JZ3gl5UvkGezztNH+PxmPFyEktW+YIKcdTeVKJs72nA+2xKGuqoAa19qAnQ7MfWRhxEOdqRtdm3 rCRJavS+472sXJBxaIliFlPC0u3Sykjm74RSVH8BrYmVpiDAr2hFcu19iCgKeul/KAD2SvXq X-Proofpoint-ORIG-GUID: lwp-Bnmmi5mst-q2WD7dSMEUMdguDqZQ X-Proofpoint-GUID: lwp-Bnmmi5mst-q2WD7dSMEUMdguDqZQ X-Authority-Analysis: v=2.4 cv=a58w9VSF c=1 sm=1 tr=0 ts=68223ef2 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=FsthO6bNoa9-iHtu9tEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-12_06,2025-05-09_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 impostorscore=0 mlxscore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505120191 On 4/28/2025 7:44 PM, Baochen Qiang wrote: > > > On 4/28/2025 11:09 PM, Jeff Hugo wrote: >> On 4/27/2025 7:37 PM, Baochen Qiang wrote: >>> >>> >>> On 4/8/2025 10:56 PM, Jeff Hugo wrote: >>>> On 4/8/2025 1:01 AM, Manivannan Sadhasivam wrote: >>>>> On Fri, Mar 28, 2025 at 10:59:13AM -0600, Jeff Hugo wrote: >>>>>> From: Pranjal Ramajor Asha Kanojiya >>>>>> >>>>>> MHI control configurations such as channel context, event context, command >>>>>> context and rings, are currently allocated individually. During MHI >>>>>> initialization MHI bus driver needs to configure the address space in >>>>>> which this control configuration resides. Since different component of the >>>>>> config is being allocated separately, only logical solution is to give the >>>>>> entire RAM address space, as they could be anywhere. >>>>>> >>>>> >>>>> This is fine... >>>> >>>> We tripped over this when experimenting with an automotive market product. The FW for that >>>> product had a rather strict interpretation of the spec, which we confirmed with the spec >>>> owner. >>>> >>>> In the specific FW implementation, the device maps the entire MHI space of shared >>>> structures in a single ATU entry. The device cannot map an entire 64-bit address space, >>>> and it expects all of the shared structures in a single compact range. >>>> >>>> This applies to the control structures, not the data buffers per the device >>>> implementation. >>>> >>>> This restriction seems backed by the spec.  I can't find a reason why the device is >>>> invalid, if limited.  I don't think this should break anything, but more on that below. >>>> >>>>> >>>>>> As per MHI specification the MHI control configuration address space should >>>>>> not be more them 4GB. >>>>>> >>>>> >>>>> Where exactly this limitation is specified in the spec? The spec supports full >>>>> 64 bit address space for the MHI control/data structures. But due to the device >>>>> DMA limitations, MHI controller drivers often use 32 bit address space. But >>>>> that's not a spec limitation. >>>> >>>> Its not the clearest thing, sadly. >>>> >>>> Document 80-NF223-11 Rev AB "MHI spec v1.2" Section 6.2 "MHI Registers" table 6-19 (page >>>> 106) - >>>> >>>> Describing MHICTRLLIMIT: "The most significant 32 bits of MHICTRLBASE and MHICTRLLIMIT >>>> registers must be equal." >>>> >>>> This means we have a 4GB range (32-bit) to play with in a 64-bit address space.  If the >>>> upper 32-bits of the 64-bit address for both the base and the limit must be the same, then >>>> the range of addresses from the base to the limit can only vary the lower 32-bits. >>>> >>>> Invalid: >>>> BASE: 0x0 >>>> LIMIT: 0xffffffff_ffffffff >>>> >>>> Valid: >>>> BASE: 0x0f_00000000 >>>> LIMIT: 0x0f_ffffffff >>> >>> as an MHI controller driver, ath11k is doing >>> >>>         mhi_ctrl->iova_start = 0; >>>         mhi_ctrl->iova_stop = ab_pci->dma_mask; >>> >>> where ab_pci->dma_mask is defined as >>> >>>         ab_pci->dma_mask = DMA_BIT_MASK(36) >>> >>> clearly this does not align with the 32bit requirement above, however there is no issue >>> hit. >>> >>> What happens if the most significant 32 bits of MHICTRLBASE and MHICTRLLIMIT is not equal? >>> SYS_ERR or RDDM? >> >> On the device we experienced this with, we would be able to transition to M0, but the >> later the device would have an internal fault and crash. > > so with this patch, MHICTRLBASE/MHICTRLLIMIT are untied from iova_start/iova_stop, meaning > current ath11k settings does not break the requirement, hence no ath11k change needed, right? I think so. -Jeff