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Mon, 12 Feb 2024 17:30:01 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41CHU0wC027045 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Feb 2024 17:30:00 GMT Received: from [10.216.55.125] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 12 Feb 2024 09:29:53 -0800 Message-ID: <13da9cd9-218d-4b3f-98f8-62edcd91a23e@quicinc.com> Date: Mon, 12 Feb 2024 22:59:50 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Pratyush Brahma Subject: Re: [PATCH v4 03/10] iommu/arm-smmu-qcom: Add support for TBUs To: CC: , , , , , , , , , , , , , , , , , , References: <20240201210529.7728-4-quic_c_gdjako@quicinc.com> Content-Language: en-US In-Reply-To: <20240201210529.7728-4-quic_c_gdjako@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9AwD145O5tY5kb5MEBPsEImeSD339Gw- X-Proofpoint-GUID: 9AwD145O5tY5kb5MEBPsEImeSD339Gw- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_14,2024-02-12_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 clxscore=1011 priorityscore=1501 mlxscore=0 malwarescore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402120133 Hi The following patch would introduce a use-after-free bug which was found during KASAN testing on qcm6490 with the patch. diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 8b04ece00420..ca806644e6eb 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -1,12 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved */ #include #include #include #include +#include #include #include "arm-smmu.h" @@ -446,6 +448,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, const struct device_node *np = smmu->dev->of_node; const struct arm_smmu_impl *impl; struct qcom_smmu *qsmmu; + int ret; if (!data) return ERR_PTR(-EINVAL); @@ -469,6 +472,12 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; + INIT_LIST_HEAD(&qsmmu->tbu_list); + mutex_init(&qsmmu->tbu_list_lock); + ret = devm_of_platform_populate(smmu->dev); // smmu has been freed by devm_krealloc() above but is being accessed here again later. This causes use-after-free bug. + if (ret) + return ERR_PTR(ret); + return &qsmmu->smmu; } Can it be done like below? qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; + INIT_LIST_HEAD(&qsmmu->tbu_list); + mutex_init(&qsmmu->tbu_list_lock); + ret = devm_of_platform_populate(qsmmu->smmu.dev);// Using the struct to which smmu was copied instead of freed ptr. Thanks, Pratyush