Re: [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 9/27/25 12:33 AM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 09:50:22AM +0300, Abel Vesa wrote:
>> On 25-09-25 20:11:11, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote:
>>>> The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort
>>>> controllers. Describe them along with display controller and the eDP
>>>> PHY. Then, attach the combo PHYs link and vco_div clocks to the Display
>>>> clock controller and link up the PHYs and DP endpoints in the graph.
>>>>
>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++-
>>>>  1 file changed, 484 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>>> index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644
>>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>
>> [...]
>>
>>>> +			mdss_dp0: displayport-controller@af54000 {
>>>> +				compatible = "qcom,glymur-dp";
>>>> +				reg = <0x0 0xaf54000 0x0 0x104>,
>>>> +				      <0x0 0xaf54200 0x0 0xc0>,
>>>> +				      <0x0 0xaf55000 0x0 0x770>,
>>>> +				      <0x0 0xaf56000 0x0 0x9c>,
>>>> +				      <0x0 0xaf57000 0x0 0x9c>;
>>>> +
>>>> +				interrupts-extended = <&mdss 12>;
>>>> +
>>>> +				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>>>> +					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>>>> +					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>>>> +					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>>>> +					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>>>
>>> No pixel1 clock?
>>
>> Will add it in next version. Everywhere.
> 
> Except DP3, if I'm not mistaken.

$ rg PIXEL1 drivers/clk/qcom/dispcc-glymur.c

1841:   [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1842:   [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1855:   [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1856:   [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1869:   [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1870:   [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,

looks like it

Konrad