From mboxrd@z Thu Jan 1 00:00:00 1970 From: Olav Haugan Subject: [PATCH v1 1/2] iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1 Date: Sun, 3 Aug 2014 17:47:43 -0700 Message-ID: <1407113264-23426-2-git-send-email-ohaugan@codeaurora.org> References: <1407113264-23426-1-git-send-email-ohaugan@codeaurora.org> Return-path: Received: from smtp.codeaurora.org ([198.145.11.231]:54604 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751974AbaHDArw (ORCPT ); Sun, 3 Aug 2014 20:47:52 -0400 In-Reply-To: <1407113264-23426-1-git-send-email-ohaugan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: will.deacon@arm.com Cc: mitchelh@codeaurora.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Olav Haugan Stage-1 context bank does not have SMMU_CBn_TCR[SL0] field. SL0 field is only applicable to stage-2 context banks. Signed-off-by: Olav Haugan --- drivers/iommu/arm-smmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ff6633d..a83ca6a 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -833,6 +833,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); break; } + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + } else { reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; } @@ -843,8 +845,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= TTBCR_EAE | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | - (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | - (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); /* MAIR0 (stage-1 only) */ -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation