[PATCH] clk: qcom: fix RCG M/N counter configuration

[PATCH] clk: qcom: fix RCG M/N counter configuration

[Archit Taneja]

Currently, a RCG's M/N counter (used for fraction division) is set to either
'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether
the corresponding rcg struct has a mnd field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is still enabled
by code even though no division takes place. Leaving the RCG in such a state
can result in improper behavior. This was observed with the DSI pixel clock RCG
when M and N were both set to 1.

Add an additional check (M != N) to enable the M/N counter only when it's needed
for fraction division.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/clk/qcom/clk-rcg2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 08b8b37..4fe9c01 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -242,7 +242,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 	mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
 	cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
 	cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
-	if (rcg->mnd_width && f->n)
+	if (rcg->mnd_width && f->n && (f->m != f->n))
 		cfg |= CFG_MODE_DUAL_EDGE;
 	ret = regmap_update_bits(rcg->clkr.regmap,
 			rcg->cmd_rcgr + CFG_REG, mask, cfg);
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Re: [PATCH] clk: qcom: fix RCG M/N counter configuration

[Stephen Boyd]

On 03/04, Archit Taneja wrote:
> Currently, a RCG's M/N counter (used for fraction division) is set to either
> 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether
> the corresponding rcg struct has a mnd field specified and a non-zero N.
> 
> In the case where M and N are the same value, the M/N counter is still enabled
> by code even though no division takes place. Leaving the RCG in such a state
> can result in improper behavior. This was observed with the DSI pixel clock RCG
> when M and N were both set to 1.
> 
> Add an additional check (M != N) to enable the M/N counter only when it's needed
> for fraction division.
> 
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---

I'm going to queue this up for 4.1 given that this isn't a new
regression. But I'll tag it for stable so that we get it into all
the stable trees.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH] clk: qcom: fix RCG M/N counter configuration

[Archit Taneja]

On 03/20/2015 10:58 AM, Stephen Boyd wrote:
> On 03/04, Archit Taneja wrote:
>> Currently, a RCG's M/N counter (used for fraction division) is set to either
>> 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether
>> the corresponding rcg struct has a mnd field specified and a non-zero N.
>>
>> In the case where M and N are the same value, the M/N counter is still enabled
>> by code even though no division takes place. Leaving the RCG in such a state
>> can result in improper behavior. This was observed with the DSI pixel clock RCG
>> when M and N were both set to 1.
>>
>> Add an additional check (M != N) to enable the M/N counter only when it's needed
>> for fraction division.
>>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>> ---
>
> I'm going to queue this up for 4.1 given that this isn't a new
> regression. But I'll tag it for stable so that we get it into all
> the stable trees.

Great, that sounds good.

Thanks,
Archit


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