From: Stephane Viau <sviau@codeaurora.org>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
robdclark@gmail.com, Stephane Viau <sviau@codeaurora.org>
Subject: [PATCH 3/5] drm/msm/mdp5: Update headers (remove enum mdp5_client_id)
Date: Mon, 9 Mar 2015 09:11:05 -0400 [thread overview]
Message-ID: <1425906667-3363-4-git-send-email-sviau@codeaurora.org> (raw)
In-Reply-To: <1425906667-3363-1-git-send-email-sviau@codeaurora.org>
This patch contains the generated header file of the following
change "drm/msm/mdp5: Get SMP client list from mdp5_cfg".
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 41 ++++++---------------------------
1 file changed, 7 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index cb931ca..b4e2624 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 29843 bytes, from 2015-03-09 12:32:38)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 28872 bytes, from 2015-03-09 12:40:51)
- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-06-02 18:31:15)
- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2015-01-23 16:20:19)
@@ -97,33 +97,6 @@ enum mdp5_pipe_bwc {
BWC_Q_MED = 2,
};
-enum mdp5_client_id {
- CID_UNUSED = 0,
- CID_VIG0_Y = 1,
- CID_VIG0_CR = 2,
- CID_VIG0_CB = 3,
- CID_VIG1_Y = 4,
- CID_VIG1_CR = 5,
- CID_VIG1_CB = 6,
- CID_VIG2_Y = 7,
- CID_VIG2_CR = 8,
- CID_VIG2_CB = 9,
- CID_DMA0_Y = 10,
- CID_DMA0_CR = 11,
- CID_DMA0_CB = 12,
- CID_DMA1_Y = 13,
- CID_DMA1_CR = 14,
- CID_DMA1_CB = 15,
- CID_RGB0 = 16,
- CID_RGB1 = 17,
- CID_RGB2 = 18,
- CID_VIG3_Y = 19,
- CID_VIG3_CR = 20,
- CID_VIG3_CB = 21,
- CID_RGB3 = 22,
- CID_MAX = 23,
-};
-
enum mdp5_cursor_format {
CURSOR_FMT_ARGB8888 = 0,
CURSOR_FMT_ARGB1555 = 2,
@@ -276,19 +249,19 @@ static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { retu
static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
{
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
}
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
{
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
}
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
{
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
}
@@ -298,19 +271,19 @@ static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { retu
static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
{
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK;
}
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
{
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK;
}
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
{
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK;
}
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-03-09 13:11 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-03 18:36 [PATCH 0/4] drm/msm: preparation for WB/DSI connectors Stephane Viau
2015-03-03 18:36 ` [PATCH 1/4] drm/msm/mdp5: Update generated header files Stephane Viau
2015-03-03 18:37 ` [PATCH] rnndb: Prepare for more interfaces support (WB, DSI) Stephane Viau
2015-03-03 18:36 ` [PATCH 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Stephane Viau
2015-03-04 6:22 ` Archit Taneja
2015-03-03 18:36 ` [PATCH 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Stephane Viau
2015-03-03 18:36 ` [PATCH 4/4] drm/msm/mdp5: Make the intf connection in config module Stephane Viau
2015-03-04 6:13 ` Archit Taneja
2015-03-04 15:44 ` "Stéphane Viau"
2015-03-05 4:03 ` Archit Taneja
2015-03-05 14:59 ` [PATCH v2 0/4] drm/msm: preparation for WB/DSI connectors Stephane Viau
2015-03-05 14:59 ` [PATCH v2 1/4] drm/msm/mdp5: Update generated header files Stephane Viau
2015-03-05 14:59 ` [PATCH v2 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Stephane Viau
2015-03-05 14:59 ` [PATCH v2 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Stephane Viau
2015-03-05 14:59 ` [PATCH v2 4/4] drm/msm/mdp5: Make the intf connection in config module Stephane Viau
2015-03-09 13:11 ` [PATCH 0/5] drm/msm: Add display configuration for msm8x16 Stephane Viau
2015-03-09 13:11 ` [PATCH 1/5] drm/msm/mdp5: Update headers (introduce MDP5 domain) Stephane Viau
2015-03-09 13:11 ` [PATCH 2/5] drm/msm/mdp5: Separate MDP5 domain from MDSS domain Stephane Viau
2015-03-09 13:11 ` Stephane Viau [this message]
2015-03-09 13:11 ` [PATCH 4/5] drm/msm/mdp5: Get SMP client list from mdp5_cfg Stephane Viau
2015-03-09 13:11 ` [PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16 Stephane Viau
2015-03-12 9:04 ` Archit Taneja
2015-03-13 19:45 ` "Stéphane Viau"
2015-03-13 19:49 ` [PATCH v3 0/4] drm/msm: preparation for WB/DSI connectors Stephane Viau
2015-03-13 19:49 ` [PATCH v3 1/4] drm/msm/mdp5: Update generated header files Stephane Viau
2015-03-13 19:49 ` [PATCH v3 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Stephane Viau
2015-03-13 19:49 ` [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Stephane Viau
2015-03-23 10:50 ` Archit Taneja
2015-03-23 22:10 ` "Stéphane Viau"
2015-03-24 4:47 ` Archit Taneja
2015-03-13 19:49 ` [PATCH v3 4/4] drm/msm/mdp5: Make the intf connection in config module Stephane Viau
2015-03-16 5:03 ` [PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16 Archit Taneja
2015-03-09 13:12 ` [PATCH 1/2] rnndb: Separate MDP5 domain from MDSS domain Stephane Viau
2015-03-09 13:12 ` [PATCH 2/2] rnndb: Do not use enum mdp5_client_id to configure SMP Stephane Viau
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