From: Stephen Boyd <sboyd@codeaurora.org>
To: Mike Turquette <mturquette@linaro.org>,
Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Viresh Kumar <viresh.kumar@linaro.org>
Subject: [PATCH v3 03/13] clk: Avoid sending high rates to downstream clocks during set_rate
Date: Fri, 20 Mar 2015 23:45:22 -0700 [thread overview]
Message-ID: <1426920332-9340-4-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1426920332-9340-1-git-send-email-sboyd@codeaurora.org>
If a clock is on and we call clk_set_rate() on it we may get into
a situation where the clock temporarily increases in rate
dramatically while we walk the tree and call .set_rate() ops. For
example, consider a case where a PLL feeds into a divider.
Initially the divider is set to divide by 1 and the PLL is
running fairly slow (100MHz). The downstream consumer of the
divider output can only handle rates =< 400 MHz, but the divider
can only choose between divisors of 1 and 4.
+-----+ +----------------+
| PLL |-->| div 1 or div 4 |---> consumer device
+-----+ +----------------+
To achieve a rate of 400MHz on the output of the divider, we
would have to set the rate of the PLL to 1.6 GHz and then divide
it by 4. The current code would set the PLL to 1.6GHz first while
the divider is still set to 1, thus causing the downstream
consumer of the clock to receive a few clock cycles of 1.6GHz
clock (far beyond it's maximum acceptable rate). We should be
changing the divider first before increasing the PLL rate to
avoid this problem.
Therefore, set the rate of any child clocks that are increasing
in rate from their current rate so that they can increase their
dividers if necessary. We assume that there isn't such a thing as
minimum rate requirements.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/clk/clk.c | 34 ++++++++++++++++++++++------------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index eb0152961d3c..0712bea649c1 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1689,21 +1689,24 @@ static struct clk_core *clk_propagate_rate_change(struct clk_core *clk,
* walk down a subtree and set the new rates notifying the rate
* change on the way
*/
-static void clk_change_rate(struct clk_core *clk)
+static void
+clk_change_rate(struct clk_core *clk, unsigned long best_parent_rate)
{
struct clk_core *child;
struct hlist_node *tmp;
unsigned long old_rate;
- unsigned long best_parent_rate = 0;
bool skip_set_rate = false;
struct clk_core *old_parent;
- old_rate = clk->rate;
+ hlist_for_each_entry(child, &clk->children, child_node) {
+ /* Skip children who will be reparented to another clock */
+ if (child->new_parent && child->new_parent != clk)
+ continue;
+ if (child->new_rate > child->rate)
+ clk_change_rate(child, clk->new_rate);
+ }
- if (clk->new_parent)
- best_parent_rate = clk->new_parent->rate;
- else if (clk->parent)
- best_parent_rate = clk->parent->rate;
+ old_rate = clk->rate;
if (clk->new_parent && clk->new_parent != clk->parent) {
old_parent = __clk_set_parent_before(clk, clk->new_parent);
@@ -1723,7 +1726,7 @@ static void clk_change_rate(struct clk_core *clk)
if (!skip_set_rate && clk->ops->set_rate)
clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
- clk->rate = clk_recalc(clk, best_parent_rate);
+ clk->rate = clk->new_rate;
if (clk->notifier_count && old_rate != clk->rate)
__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
@@ -1736,12 +1739,13 @@ static void clk_change_rate(struct clk_core *clk)
/* Skip children who will be reparented to another clock */
if (child->new_parent && child->new_parent != clk)
continue;
- clk_change_rate(child);
+ if (child->new_rate != child->rate)
+ clk_change_rate(child, clk->new_rate);
}
/* handle the new child who might not be in clk->children yet */
- if (clk->new_child)
- clk_change_rate(clk->new_child);
+ if (clk->new_child && clk->new_child->new_rate != clk->new_child->rate)
+ clk_change_rate(clk->new_child, clk->new_rate);
}
static int clk_core_set_rate_nolock(struct clk_core *clk,
@@ -1750,6 +1754,7 @@ static int clk_core_set_rate_nolock(struct clk_core *clk,
struct clk_core *top, *fail_clk;
unsigned long rate = req_rate;
int ret = 0;
+ unsigned long parent_rate;
if (!clk)
return 0;
@@ -1775,8 +1780,13 @@ static int clk_core_set_rate_nolock(struct clk_core *clk,
return -EBUSY;
}
+ if (top->parent)
+ parent_rate = top->parent->rate;
+ else
+ parent_rate = 0;
+
/* change the rates */
- clk_change_rate(top);
+ clk_change_rate(top, parent_rate);
clk->req_rate = req_rate;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-03-21 6:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-21 6:45 [PATCH v3 00/13] Krait clocks + Krait CPUfreq Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 01/13] ARM: Add Krait L2 register accessor functions Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 02/13] clk: mux: Split out register accessors for reuse Stephen Boyd
2015-03-21 6:45 ` Stephen Boyd [this message]
2015-03-21 6:45 ` [PATCH v3 04/13] clk: Add safe switch hook Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 05/13] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 06/13] clk: qcom: Add HFPLL driver Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 07/13] clk: qcom: Add MSM8960/APQ8064's HFPLLs Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 08/13] clk: qcom: Add IPQ806X's HFPLLs Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 09/13] clk: qcom: Add support for Krait clocks Stephen Boyd
[not found] ` <1426920332-9340-1-git-send-email-sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-03-21 6:45 ` [PATCH v3 10/13] clk: qcom: Add KPSS ACC/GCC driver Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 11/13] clk: qcom: Add Krait clock controller driver Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 12/13] cpufreq: Add module to register cpufreq on Krait CPUs Stephen Boyd
2015-03-21 6:45 ` [PATCH v3 13/13] ARM: dts: qcom: Add necessary DT data for Krait cpufreq Stephen Boyd
2015-04-02 6:17 ` [PATCH v3 00/13] Krait clocks + Krait CPUfreq Pavel Machek
2015-04-02 6:18 ` Pavel Machek
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