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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-64b90f53c51sm44266784a12.3.2026.01.02.04.00.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Jan 2026 04:00:52 -0800 (PST) Message-ID: <1440e47e-2d7b-4d49-97c4-a717fadd3fb6@oss.qualcomm.com> Date: Fri, 2 Jan 2026 13:00:50 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/9] remoteproc: qcom_q6v5_mss: Add MDM9607 To: Bryan O'Donoghue , barnabas.czeman@mainlining.org Cc: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251231-mss-v3-0-f80e8fade9ec@mainlining.org> <20251231-mss-v3-3-f80e8fade9ec@mainlining.org> <6bfc790d-b0da-4c5b-bd2d-ceed9a75bb24@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=GupPO01C c=1 sm=1 tr=0 ts=6957b377 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=OuZLqq7tAAAA:8 a=Tc7beqaULkBTywLjy2IA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=AKGiAy9iJ-JzxKVHQNES:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTAyMDEwNSBTYWx0ZWRfXz6Z41bplfDUP et7nGV5UcCTZdMumKpzJSInfsXSYZzJvoBIHuTiTrHDhVLlhkebbuRk4mSXqzpCnLPS7NQaYPvY INUmLWzwAegHsfIgBCbTAKbu2qbQR4Dj7btvGT5tkRALaymfTsYukRVO6pNsZi/5rV10G9ej4AV n2QbEwOoZ4lkTyblFllNxrXwrE+gUU7oS9xijNr9d7pazQDdPMR8dVOh4tRTVwhNZ1QDEdGFkBd 0pCLVxztd1l6g2nmACuD9PcfY5UPjgLuyp2+bmYKwa9Qi2/WDojW5+GzhkUJf8k5ePWsffH7Zaw xqNlqTq1Zxoj/Bsr/8cjACfPJn8emKuSyfZlEqGawJ5IzW1HxhmfQRy8S0jz9Wt0KNiEJQnS+U5 J3UQwIXazKGKHsCTpU9uBwLWGjo5ElGq16l8NTMLfNGolzyXepBxcYc2FM5Dk9OxEwaY+yK1pAN NQs2zcPUCwSxRV2FVKQ== X-Proofpoint-GUID: 6cb_-KEKGVJVHYHOT_TfdURDsAS1xi7i X-Proofpoint-ORIG-GUID: 6cb_-KEKGVJVHYHOT_TfdURDsAS1xi7i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-02_01,2025-12-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601020105 On 1/1/26 9:58 PM, Bryan O'Donoghue wrote: > On 01/01/2026 13:50, barnabas.czeman@mainlining.org wrote: >>>> +                for (; i >= 0; i--) { >>>> +                    val |= BIT(i); >>>> +                    writel(val, qproc->reg_base + mem_pwr_ctl); >>>> +                    /* >>>> +                     * Read back value to ensure the write is done then >>>> +                     * wait for 1us for both memory peripheral and data >>>> +                     * array to turn on. >>>> +                     */ >>>> +                    val |= readl(qproc->reg_base + mem_pwr_ctl); >>>> +                    udelay(1); >>> Isn't the logic here inverted ? >>> >>> i.e. you've written a thing and ostensibly require a delay for that >>> thing to take effect, the power to switch on in this case. >>> >>> It makes more sense to write, delay and read back rather than write, >>> readback and delay surely... >> This is the original reset sequence without modification, i have just >> moved it in a else case when it is not an MDM9607, MSM8917 or MSM8937. > > Doesn't make it correct, we fix upstream logic bugs all the time... > > For example a read-back to ensure write completion is only required for posted memory transactions. > > Is this a posted write ? > > Is there an io-fabric in the world which exceeds 1 microsecond to perform a write transaction ? Writes on arm64 aren't usually observable from the remote endpoint when you would expect them to, they can be buffered unless there's an explicit readback right afterwards (which creates a dependency that the processor will fulfill) Now I don't like that this driver is going val |= BIT(i); writel(val, foo); // val is "altered" but not really val |= readl(foo); I didn't notice we were just doing a readback for the sake of a readback in the last revision. MDM9607 should most definitely have it too.. Perhaps I should have just read the comment Konrad