From mboxrd@z Thu Jan 1 00:00:00 1970 From: Georgi Djakov Subject: [PATCH v3 7/8] clk: qcom: msm8916: Use RPMCC if it is enabled Date: Tue, 20 Oct 2015 19:57:59 +0300 Message-ID: <1445360280-2347-8-git-send-email-georgi.djakov@linaro.org> References: <1445360280-2347-1-git-send-email-georgi.djakov@linaro.org> Return-path: Received: from mail-wi0-f169.google.com ([209.85.212.169]:38499 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752791AbbJTQ6p (ORCPT ); Tue, 20 Oct 2015 12:58:45 -0400 Received: by wicll6 with SMTP id ll6so38082033wic.1 for ; Tue, 20 Oct 2015 09:58:44 -0700 (PDT) In-Reply-To: <1445360280-2347-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: sboyd@codeaurora.org, agross@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, bjorn.andersson@sonymobile.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org The RPM clock controller driver takes care of registering the xo clock. Do not register it in this driver if RPM is enabled. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/gcc-msm8916.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 4bb7d8415ba7..3e1062fed230 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -3359,13 +3359,15 @@ static int gcc_msm8916_probe(struct platform_device *pdev) struct clk *clk; struct device *dev = &pdev->dev; - /* Temporary until RPM clocks supported */ - clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - clk_register_fixed_rate(dev, "sleep_clk_src", NULL, - CLK_IS_ROOT, 32768); + if (!IS_ENABLED(CONFIG_QCOM_RPMCC)) { + /* RPM clocks are not enabled */ + clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + clk_register_fixed_rate(dev, "sleep_clk_src", NULL, + CLK_IS_ROOT, 32768); + } return qcom_cc_probe(pdev, &gcc_msm8916_desc); }