From: Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Sricharan <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: [PATCH 1/2] iommu/msm: resume device after fault
Date: Fri, 12 Aug 2016 11:29:06 -0400 [thread overview]
Message-ID: <1471015747-569-1-git-send-email-robdclark@gmail.com> (raw)
We need to disable stall on memory access after a fault, otherwise the
device using the iommu will be perma-wedged with no access to memory.
This was causing drm/msm to be unable to recover the gpu after an iommu
fault.
Signed-off-by: Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/iommu/msm_iommu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
index b09692b..f6f596f 100644
--- a/drivers/iommu/msm_iommu.c
+++ b/drivers/iommu/msm_iommu.c
@@ -628,6 +628,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
pr_err("Interesting registers:\n");
print_ctx_regs(iommu->base, i);
SET_FSR(iommu->base, i, 0x4000000F);
+ SET_RESUME(iommu->base, i, 1);
}
}
__disable_clocks(iommu);
--
2.7.4
next reply other threads:[~2016-08-12 15:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-12 15:29 Rob Clark [this message]
[not found] ` <1471015747-569-1-git-send-email-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-08-12 15:29 ` [PATCH 2/2] iommu/msm: wire up fault handling Rob Clark
[not found] ` <1471015747-569-2-git-send-email-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-08-12 16:17 ` Sricharan
2016-08-12 16:39 ` Rob Clark
2016-08-12 15:50 ` [PATCH 1/2] iommu/msm: resume device after fault Sricharan
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