[PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver

[PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver

[Abhishek Sahu]

These patches are related to Qualcomm IPQ4019 GCC (Global Clock
Controller) driver code mainly adding the nodes for clock marked
as fixed in current IPQ4019 clock driver and support for multiple
CPU frequencies.

[V3]

   1. Addressed the review comments given in v2 patches.
   2. Replaced the do_div with normal division.
   3. Marked the PCNOC node as critical.
   4. Modified the frequency values for the recent change done
      in IPQ4019 bootloader.
   5. Changed the i2c node frequency table for 19.05 MHz clock.

[V2]

   1. Removed the fixed clock references and add the same as clock nodes
   with recalc_rate operation.
   2. Added all the supported cpu frequencies in frequency table.

Abhishek Sahu (7):
  clk: qcom: ipq4019: Added the clock nodes and operations for pll
  clk: qcom: ipq4019: Added the apss cpu pll divider clock node
  clk: qcom: ipq4019: Added the nodes for pcnoc
  clk: qcom: ipq4019: Added all the frequencies for apps cpu
  clk: qcom: ipq4019: corrected sdcc frequency and parent name
  clk: qcom: ipq4019: changed the frequency value for ddr pll
  clk: qcom: ipq4019: changed i2c freq table

 drivers/clk/qcom/gcc-ipq4019.c               | 489 +++++++++++++++++++++++++--
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |  11 +
 2 files changed, 477 insertions(+), 23 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 1/7] clk: qcom: ipq4019: Added the clock nodes and operations for pll

[Abhishek Sahu]

The current ipq4019 clock driver registered the PLL clocks and
dividers as fixed clock. These fixed clock needs to be removed
from driver probe function and same need to be registered with
clock framework. These PLL clocks should be programmed only
once and the same are being programmed already by the boot
loader so the set rate operation is not required for these
clocks. Only the rate can be calculated by clock operations
in clock driver file so this patch adds the same.

The PLL takes the reference clock from XO and generates the
intermediate VCO frequency. This VCO frequency will be divided
down by different PLL internal dividers. Some of the PLL
internal dividers are fixed while other are programmable.

This patch does the following changes.
1. Operation for calculating PLL intermediate VCO frequency by
   reading the reference clock divider and feedback divider from
   register. Since VCO frequency falls outside the limit of
   unsigned long for IPQ4019, so this operation will return the
   VCO frequency in kHz.

2. Operation for calculating the internal PLL divider clock
   frequency. Clock Divider node should give either fixed
   divider value or divider table(maps the register divider
   value to actual divider value).

3. Adds and registers clock nodes for VCO(APPS DDR PLL and FE
   PLL) and PLL internal dividers(SDCC, FEPLL 500 MHz, FEPLL
   200 MHz, FEPLL 125 MHz, FEPLL 125 MHz with delay,
   programmable WCSS 2G and 5G).

4. Changes the regmap limit from 0x2dffff to 0x2ffff for
   supporting the PLL registers read.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c               | 292 ++++++++++++++++++++++++++-
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |   9 +
 2 files changed, 290 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 3cd1af0..9251457 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -28,6 +28,16 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "clk-regmap-divider.h"
+
+#define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\
+					struct clk_regmap_div, clkr)
+
+#define to_clk_pll_div(_hw) container_of((to_clk_regmap_div(_hw)),\
+						struct clk_pll_div, cdiv)
+
+#define to_clk_pll_vco(_hw) container_of((to_clk_regmap_div(_hw)),\
+						struct clk_pll_vco, cdiv)
 
 enum {
 	P_XO,
@@ -40,6 +50,35 @@ enum {
 	P_DDRPLLAPSS,
 };
 
+/*
+ * struct clk_pll_vco - vco feedback divider corresponds to PLL_DIV register
+ * @fdbkdiv_shift: lowest bit for FDBKDIV
+ * @fdbkdiv_width: number of bits in FDBKDIV
+ * @cdiv: divider values for PLL_DIV
+ */
+struct clk_pll_vco {
+	u32 fdbkdiv_shift;
+	u32 fdbkdiv_width;
+	struct clk_regmap_div cdiv;
+};
+
+/*
+ * struct clk_pll_div - clk divider corresponds to PLL_DIV register
+ * @fixed_div: fixed divider value if divider is fixed
+ * @parent_map: map from software's parent index to hardware's src_sel field
+ * @cdiv: divider values for PLL_DIV
+ * @div_table: mapping for actual divider value to register divider value
+ *             in case of non fixed divider
+ * @freq_tbl: frequency table
+ */
+struct clk_pll_div {
+	u32 fixed_div;
+	const u8 *parent_map;
+	struct clk_regmap_div cdiv;
+	const struct clk_div_table *div_table;
+	const struct freq_tbl *freq_tbl;
+};
+
 static struct parent_map gcc_xo_200_500_map[] = {
 	{ P_XO, 0 },
 	{ P_FEPLL200, 1 },
@@ -1155,6 +1194,238 @@ static struct clk_branch gcc_wcss5g_rtc_clk = {
 	},
 };
 
+/*
+ * Calculates the rate from parent rate and divider and round the rate
+ * in MHz. This function takes the parent rate in kHz and returns the
+ * rate in Hz.
+ */
+static unsigned long clk_calc_divider_rate(unsigned long parent_rate,
+				unsigned int div)
+{
+	u32 rate;
+
+	rate = parent_rate / div;
+
+	/*
+	 * This rate is in kHz and returned value should be rounded
+	 * in MHz. So divide the value with 1000 and multiply it with
+	 * 1000(rate value was divided with 1000) * 1000(kHz to MHz).
+	 */
+	rate /= 1000;
+	rate *= 1000000;
+
+	return rate;
+}
+
+/*
+ * Calculates the VCO rate for PLL.
+ * VCO rate value is greater than unsigned long limit. Since this is an
+ * intermediate clock node for actual PLL dividers, so it returns the
+ * rate in kHz. The child nodes will return the value in Hz after its
+ * divide operation.
+ */
+static unsigned long clk_regmap_vco_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
+{
+	struct clk_pll_vco *rcg = to_clk_pll_vco(hw);
+	u32 fdbkdiv, refclkdiv, cdiv, vco;
+
+	regmap_read(rcg->cdiv.clkr.regmap, rcg->cdiv.reg, &cdiv);
+	refclkdiv = (cdiv >> rcg->cdiv.shift) & (BIT(rcg->cdiv.width) - 1);
+	fdbkdiv = (cdiv >> rcg->fdbkdiv_shift) & (BIT(rcg->fdbkdiv_width) - 1);
+
+	vco = parent_rate / refclkdiv;
+	vco /= 1000;
+	vco *= 2;
+	vco *= fdbkdiv;
+
+	return vco;
+}
+
+static const struct clk_ops clk_regmap_vco_ops = {
+	.recalc_rate = clk_regmap_vco_recalc_rate,
+};
+
+static struct clk_pll_vco gcc_apps_ddrpll_vco = {
+	.fdbkdiv_shift = 16,
+	.fdbkdiv_width = 8,
+	.cdiv.reg = 0x2e020,
+	.cdiv.shift = 24,
+	.cdiv.width = 5,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_apps_ddrpll_vco",
+			.parent_names = (const char *[]){
+				"xo",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_vco_ops,
+		},
+	},
+};
+
+static struct clk_pll_vco gcc_fepll_vco = {
+	.fdbkdiv_shift = 16,
+	.fdbkdiv_width = 8,
+	.cdiv.reg = 0x2f020,
+	.cdiv.shift = 24,
+	.cdiv.width = 5,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_fepll_vco",
+			.parent_names = (const char *[]){
+				"xo",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_vco_ops,
+		},
+	},
+};
+
+/*
+ * Calculates the rate for PLL divider.
+ * If the divider value is not fixed then it gets the actual divider value
+ * from divider table. Then, it calculate the clock rate by dividing the
+ * parent rate with actual divider value.
+ */
+static unsigned long clk_regmap_clk_div_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_pll_div *rcg = to_clk_pll_div(hw);
+	u32 cdiv, pre_div = 1;
+	const struct clk_div_table *clkt;
+
+	if (rcg->fixed_div) {
+		pre_div = rcg->fixed_div;
+	} else {
+		regmap_read(rcg->cdiv.clkr.regmap, rcg->cdiv.reg, &cdiv);
+		cdiv = (cdiv >> rcg->cdiv.shift) & (BIT(rcg->cdiv.width) - 1);
+
+		for (clkt = rcg->div_table; clkt->div; clkt++) {
+			if (clkt->val == cdiv)
+				pre_div = clkt->div;
+		}
+	}
+
+	return clk_calc_divider_rate(parent_rate, pre_div);
+};
+
+static const struct clk_ops clk_regmap_clk_div_ops = {
+	.recalc_rate = clk_regmap_clk_div_recalc_rate,
+};
+
+static struct clk_pll_div gcc_apps_sdcc_clk = {
+	.fixed_div = 28,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "ddrpllsdcc",
+			.parent_names = (const char *[]){
+				"gcc_apps_ddrpll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+};
+
+static struct clk_pll_div gcc_fepll125_clk = {
+	.fixed_div = 32,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "fepll125",
+			.parent_names = (const char *[]){
+				"gcc_fepll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+};
+
+static struct clk_pll_div gcc_fepll125dly_clk = {
+	.fixed_div = 32,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "fepll125dly",
+			.parent_names = (const char *[]){
+				"gcc_fepll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+};
+
+static struct clk_pll_div gcc_fepll200_clk = {
+	.fixed_div = 20,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "fepll200",
+			.parent_names = (const char *[]){
+				"gcc_fepll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+};
+
+static struct clk_pll_div gcc_fepll500_clk = {
+	.fixed_div = 8,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "fepll500",
+			.parent_names = (const char *[]){
+				"gcc_fepll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+};
+
+static const struct clk_div_table fepllwcss_clk_div_table[] = {
+	{ 0, 15 },
+	{ 1, 16 },
+	{ 2, 18 },
+	{ 3, 20 },
+	{ },
+};
+
+static struct clk_pll_div gcc_fepllwcss2g_clk = {
+	.cdiv.reg = 0x2f020,
+	.cdiv.shift = 8,
+	.cdiv.width = 2,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "fepllwcss2g",
+			.parent_names = (const char *[]){
+				"gcc_fepll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+	.div_table = fepllwcss_clk_div_table
+};
+
+static struct clk_pll_div gcc_fepllwcss5g_clk = {
+	.cdiv.reg = 0x2f020,
+	.cdiv.shift = 12,
+	.cdiv.width = 2,
+	.cdiv.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "fepllwcss5g",
+			.parent_names = (const char *[]){
+				"gcc_fepll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_clk_div_ops,
+		},
+	},
+	.div_table = fepllwcss_clk_div_table
+};
+
 static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[AUDIO_CLK_SRC] = &audio_clk_src.clkr,
 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -1215,6 +1486,15 @@ static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
 	[GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
 	[GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
+	[GCC_APPS_DDRPLL_VCO] = &gcc_apps_ddrpll_vco.cdiv.clkr,
+	[GCC_FEPLL_VCO] = &gcc_fepll_vco.cdiv.clkr,
+	[GCC_SDCC_PLLDIV_CLK] = &gcc_apps_sdcc_clk.cdiv.clkr,
+	[GCC_FEPLL125_CLK] = &gcc_fepll125_clk.cdiv.clkr,
+	[GCC_FEPLL125DLY_CLK] = &gcc_fepll125dly_clk.cdiv.clkr,
+	[GCC_FEPLL200_CLK] = &gcc_fepll200_clk.cdiv.clkr,
+	[GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr,
+	[GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,
+	[GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
@@ -1295,7 +1575,7 @@ static const struct regmap_config gcc_ipq4019_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
-	.max_register	= 0x2dfff,
+	.max_register	= 0x2ffff,
 	.fast_io	= true,
 };
 
@@ -1315,16 +1595,6 @@ MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
 
 static int gcc_ipq4019_probe(struct platform_device *pdev)
 {
-	struct device *dev = &pdev->dev;
-
-	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
-	clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
-
 	return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
 }
 
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
index 6240e5b..cd0cd23 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -81,6 +81,15 @@
 #define GCC_WCSS5G_CLK					62
 #define GCC_WCSS5G_REF_CLK				63
 #define GCC_WCSS5G_RTC_CLK				64
+#define GCC_APPS_DDRPLL_VCO				65
+#define GCC_SDCC_PLLDIV_CLK				66
+#define GCC_FEPLL_VCO					67
+#define GCC_FEPLL125_CLK				68
+#define GCC_FEPLL125DLY_CLK				69
+#define GCC_FEPLL200_CLK				70
+#define GCC_FEPLL500_CLK				71
+#define GCC_FEPLL_WCSS2G_CLK				72
+#define GCC_FEPLL_WCSS5G_CLK				73
 
 #define WIFI0_CPU_INIT_RESET				0
 #define WIFI0_RADIO_SRIF_RESET				1
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 1/7] clk: qcom: ipq4019: Added the clock nodes and operations for pll

[Stephen Boyd]

On 09/21, Abhishek Sahu wrote:
> The current ipq4019 clock driver registered the PLL clocks and
> dividers as fixed clock. These fixed clock needs to be removed
> from driver probe function and same need to be registered with
> clock framework. These PLL clocks should be programmed only
> once and the same are being programmed already by the boot
> loader so the set rate operation is not required for these
> clocks. Only the rate can be calculated by clock operations
> in clock driver file so this patch adds the same.
> 
> The PLL takes the reference clock from XO and generates the
> intermediate VCO frequency. This VCO frequency will be divided
> down by different PLL internal dividers. Some of the PLL
> internal dividers are fixed while other are programmable.
> 
> This patch does the following changes.

This should never be in the commit text. What a patch does should
be obvious from the patch itself. Why we're doing it is much more
important to express.

> 1. Operation for calculating PLL intermediate VCO frequency by
>    reading the reference clock divider and feedback divider from
>    register. Since VCO frequency falls outside the limit of
>    unsigned long for IPQ4019, so this operation will return the
>    VCO frequency in kHz.
> 
> 2. Operation for calculating the internal PLL divider clock
>    frequency. Clock Divider node should give either fixed
>    divider value or divider table(maps the register divider
>    value to actual divider value).
> 
> 3. Adds and registers clock nodes for VCO(APPS DDR PLL and FE
>    PLL) and PLL internal dividers(SDCC, FEPLL 500 MHz, FEPLL
>    200 MHz, FEPLL 125 MHz, FEPLL 125 MHz with delay,
>    programmable WCSS 2G and 5G).
> 
> 4. Changes the regmap limit from 0x2dffff to 0x2ffff for
>    supporting the PLL registers read.

Yep that's obvious from the patch.

> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/clk/qcom/gcc-ipq4019.c               | 292 ++++++++++++++++++++++++++-
>  include/dt-bindings/clock/qcom,gcc-ipq4019.h |   9 +
>  2 files changed, 290 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
> index 3cd1af0..9251457 100644
> --- a/drivers/clk/qcom/gcc-ipq4019.c
> +++ b/drivers/clk/qcom/gcc-ipq4019.c
> @@ -28,6 +28,16 @@
>  #include "clk-rcg.h"
>  #include "clk-branch.h"
>  #include "reset.h"
> +#include "clk-regmap-divider.h"
> +
> +#define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\
> +					struct clk_regmap_div, clkr)
> +
> +#define to_clk_pll_div(_hw) container_of((to_clk_regmap_div(_hw)),\
> +						struct clk_pll_div, cdiv)
> +
> +#define to_clk_pll_vco(_hw) container_of((to_clk_regmap_div(_hw)),\
> +						struct clk_pll_vco, cdiv)
>  

Please remove double parenthesis around to_clk_regmap_div()
unlesss there's some reason for that?

>  enum {
>  	P_XO,
> @@ -40,6 +50,35 @@ enum {
>  	P_DDRPLLAPSS,
>  };
>  
> +/*
> + * struct clk_pll_vco - vco feedback divider corresponds to PLL_DIV register
> + * @fdbkdiv_shift: lowest bit for FDBKDIV
> + * @fdbkdiv_width: number of bits in FDBKDIV
> + * @cdiv: divider values for PLL_DIV
> + */
> +struct clk_pll_vco {
> +	u32 fdbkdiv_shift;
> +	u32 fdbkdiv_width;
> +	struct clk_regmap_div cdiv;
> +};
> +
> +/*
> + * struct clk_pll_div - clk divider corresponds to PLL_DIV register
> + * @fixed_div: fixed divider value if divider is fixed
> + * @parent_map: map from software's parent index to hardware's src_sel field
> + * @cdiv: divider values for PLL_DIV
> + * @div_table: mapping for actual divider value to register divider value
> + *             in case of non fixed divider
> + * @freq_tbl: frequency table
> + */
> +struct clk_pll_div {

s/clk_pll_div/clk_fepll/?

> +	u32 fixed_div;
> +	const u8 *parent_map;
> +	struct clk_regmap_div cdiv;
> +	const struct clk_div_table *div_table;
> +	const struct freq_tbl *freq_tbl;
> +};
> +
>  static struct parent_map gcc_xo_200_500_map[] = {
>  	{ P_XO, 0 },
>  	{ P_FEPLL200, 1 },
> @@ -1155,6 +1194,238 @@ static struct clk_branch gcc_wcss5g_rtc_clk = {
>  	},
>  };
>  
> +/*
> + * Calculates the rate from parent rate and divider and round the rate
> + * in MHz. This function takes the parent rate in kHz and returns the
> + * rate in Hz.
> + */
> +static unsigned long clk_calc_divider_rate(unsigned long parent_rate,

Umm... parent_rate should be in Hz here.

> +				unsigned int div)
> +{
> +	u32 rate;
> +
> +	rate = parent_rate / div;
> +
> +	/*
> +	 * This rate is in kHz and returned value should be rounded
> +	 * in MHz. So divide the value with 1000 and multiply it with
> +	 * 1000(rate value was divided with 1000) * 1000(kHz to MHz).
> +	 */
> +	rate /= 1000;
> +	rate *= 1000000;

Is this some complicated mechanism to round down to the nearest
MHz? Why? Also, can this function be rolled into the single
caller?

> +
> +	return rate;
> +}
> +
> +/*
> + * Calculates the VCO rate for PLL.
> + * VCO rate value is greater than unsigned long limit. Since this is an
> + * intermediate clock node for actual PLL dividers, so it returns the
> + * rate in kHz. The child nodes will return the value in Hz after its
> + * divide operation.
> + */
> +static unsigned long clk_regmap_vco_recalc_rate(struct clk_hw *hw,
> +						unsigned long parent_rate)
> +{
> +	struct clk_pll_vco *rcg = to_clk_pll_vco(hw);
> +	u32 fdbkdiv, refclkdiv, cdiv, vco;
> +
> +	regmap_read(rcg->cdiv.clkr.regmap, rcg->cdiv.reg, &cdiv);
> +	refclkdiv = (cdiv >> rcg->cdiv.shift) & (BIT(rcg->cdiv.width) - 1);
> +	fdbkdiv = (cdiv >> rcg->fdbkdiv_shift) & (BIT(rcg->fdbkdiv_width) - 1);
> +
> +	vco = parent_rate / refclkdiv;
> +	vco /= 1000;
> +	vco *= 2;
> +	vco *= fdbkdiv;
> +
> +	return vco;

Urgh. Bad. We shouldn't be changing the units in this case
because unsigned long is limiting. One solution is to make a
"mega clock" and do the division as well in one recalc_rate
function. That circumvents the need to pass large frequencies as
khz to get around the limit of unsigned long on 32 bit platforms.
Otherwise, we need to go ahead and make the "rate" member of
struct clk_rate_request be u64 and then this problem doesn't
exist inside the clk drivers (just with the consumer APIs).

> +}
> +
> +static const struct clk_ops clk_regmap_vco_ops = {
> +	.recalc_rate = clk_regmap_vco_recalc_rate,
> +};
> +
> +static struct clk_pll_vco gcc_apps_ddrpll_vco = {
> +	.fdbkdiv_shift = 16,
> +	.fdbkdiv_width = 8,
> +	.cdiv.reg = 0x2e020,
> +	.cdiv.shift = 24,
> +	.cdiv.width = 5,
> +	.cdiv.clkr = {
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_apps_ddrpll_vco",
> +			.parent_names = (const char *[]){
> +				"xo",
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_regmap_vco_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_pll_vco gcc_fepll_vco = {
> +	.fdbkdiv_shift = 16,
> +	.fdbkdiv_width = 8,
> +	.cdiv.reg = 0x2f020,
> +	.cdiv.shift = 24,
> +	.cdiv.width = 5,
> +	.cdiv.clkr = {
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_fepll_vco",
> +			.parent_names = (const char *[]){
> +				"xo",
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_regmap_vco_ops,
> +		},
> +	},
> +};
> +
> +/*
> + * Calculates the rate for PLL divider.
> + * If the divider value is not fixed then it gets the actual divider value
> + * from divider table. Then, it calculate the clock rate by dividing the
> + * parent rate with actual divider value.
> + */
> +static unsigned long clk_regmap_clk_div_recalc_rate(struct clk_hw *hw,
> +					   unsigned long parent_rate)
> +{
> +	struct clk_pll_div *rcg = to_clk_pll_div(hw);
> +	u32 cdiv, pre_div = 1;
> +	const struct clk_div_table *clkt;
> +
> +	if (rcg->fixed_div) {
> +		pre_div = rcg->fixed_div;
> +	} else {
> +		regmap_read(rcg->cdiv.clkr.regmap, rcg->cdiv.reg, &cdiv);
> +		cdiv = (cdiv >> rcg->cdiv.shift) & (BIT(rcg->cdiv.width) - 1);
> +
> +		for (clkt = rcg->div_table; clkt->div; clkt++) {
> +			if (clkt->val == cdiv)
> +				pre_div = clkt->div;
> +		}
> +	}
> +
> +	return clk_calc_divider_rate(parent_rate, pre_div);
> +};
> +
> +static const struct clk_ops clk_regmap_clk_div_ops = {

clk_fepll_div_ops?

> +	.recalc_rate = clk_regmap_clk_div_recalc_rate,
> +};
> +
> +static struct clk_pll_div gcc_apps_sdcc_clk = {
> +	.fixed_div = 28,
> +	.cdiv.clkr = {
> +		.hw.init = &(struct clk_init_data){
> +			.name = "ddrpllsdcc",
> +			.parent_names = (const char *[]){
> +				"gcc_apps_ddrpll_vco",
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_regmap_clk_div_ops,
> +		},
> +	},
> +};
> +

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 2/7] clk: qcom: ipq4019: Added the apss cpu pll divider clock node

[Abhishek Sahu]

The current ipq4019 clock driver does not have support for all
the frequency supported by APPS CPU. APPS CPU frequency is
provided with APSS CPU PLL divider which divides down the VCO
frequency. This divider is nonlinear and specific to IPQ4019
so the standard divider code cannot be used for this.

This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c               | 127 ++++++++++++++++++++++++++-
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |   1 +
 2 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 9251457..74f7ba8 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -20,6 +20,7 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
+#include <linux/delay.h>
 
 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
 
@@ -581,6 +582,7 @@ static struct clk_rcg2 apps_clk_src = {
 		.parent_names = gcc_xo_ddr_500_200,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1283,7 +1285,129 @@ static struct clk_pll_vco gcc_fepll_vco = {
 };
 
 /*
- * Calculates the rate for PLL divider.
+ * Round rate function for APPS CPU PLL Clock divider.
+ * It looks up the frequency table and returns the next higher frequency
+ * supported in hardware.
+ */
+static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *p_rate)
+{
+	struct clk_pll_div *rcg = to_clk_pll_div(hw);
+	struct clk_hw *p_hw;
+	const struct freq_tbl *f;
+
+	f = qcom_find_freq(rcg->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	p_hw = clk_hw_get_parent_by_index(hw, f->src);
+	*p_rate = clk_hw_get_rate(p_hw);
+
+	return f->freq;
+};
+
+/*
+ * Clock set rate function for APPS CPU PLL Clock divider.
+ * It looks up the frequency table and updates the PLL divider to corresponding
+ * divider value.
+ */
+static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct clk_pll_div *rcg = to_clk_pll_div(hw);
+	const struct freq_tbl *f;
+	u32 mask;
+	int ret;
+
+	f = qcom_find_freq(rcg->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	mask = (BIT(rcg->cdiv.width) - 1) << rcg->cdiv.shift;
+	ret = regmap_update_bits(rcg->cdiv.clkr.regmap,
+				rcg->cdiv.reg, mask,
+				f->pre_div << rcg->cdiv.shift);
+	/*
+	 * There is no status bit which can be checked for successful CPU
+	 * divider update operation so using delay for the same.
+	 */
+	udelay(1);
+
+	return 0;
+};
+
+/*
+ * Clock frequency calculation function for APPS CPU PLL Clock divider.
+ * This clock divider is nonlinear so this function calculates the actual
+ * divider and returns the output frequency by dividing VCO Frequency
+ * with this actual divider value.
+ */
+static unsigned long clk_cpu_div_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_pll_div *rcg = to_clk_pll_div(hw);
+	u32 cdiv, pre_div;
+
+	regmap_read(rcg->cdiv.clkr.regmap, rcg->cdiv.reg, &cdiv);
+	cdiv = (cdiv >> rcg->cdiv.shift) & (BIT(rcg->cdiv.width) - 1);
+
+	/*
+	 * Some dividers have value in 0.5 fraction so multiply both VCO
+	 * frequency(parent_rate) and pre_div with 2 to make integer
+	 * calculation.
+	 */
+	if (cdiv > 10)
+		pre_div = (cdiv + 1) * 2;
+	else
+		pre_div = cdiv + 12;
+
+	return clk_calc_divider_rate(parent_rate * 2, pre_div);
+};
+
+static const struct clk_ops clk_regmap_cpu_div_ops = {
+	.round_rate = clk_cpu_div_round_rate,
+	.set_rate = clk_cpu_div_set_rate,
+	.recalc_rate = clk_cpu_div_recalc_rate,
+};
+
+static const struct freq_tbl ftbl_apps_ddr_pll[] = {
+	{ 380000000, P_XO, 0xd, 0, 0 },
+	{ 409000000, P_XO, 0xc, 0, 0 },
+	{ 444000000, P_XO, 0xb, 0, 0 },
+	{ 484000000, P_XO, 0xa, 0, 0 },
+	{ 507000000, P_XO, 0x9, 0, 0 },
+	{ 532000000, P_XO, 0x8, 0, 0 },
+	{ 560000000, P_XO, 0x7, 0, 0 },
+	{ 592000000, P_XO, 0x6, 0, 0 },
+	{ 626000000, P_XO, 0x5, 0, 0 },
+	{ 666000000, P_XO, 0x4, 0, 0 },
+	{ 710000000, P_XO, 0x3, 0, 0 },
+	{ 761000000, P_XO, 0x2, 0, 0 },
+	{ 819000000, P_XO, 0x1, 0, 0 },
+	{ 888000000, P_XO, 0x0, 0, 0 },
+	{ }
+};
+
+static struct clk_pll_div gcc_apps_cpu_plldiv_clk = {
+	.cdiv.reg = 0x2e020,
+	.cdiv.shift = 4,
+	.cdiv.width = 4,
+	.cdiv.clkr = {
+		.enable_reg = 0x2e000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "ddrpllapss",
+			.parent_names = (const char *[]){
+				"gcc_apps_ddrpll_vco",
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_cpu_div_ops,
+		},
+	},
+	.freq_tbl = ftbl_apps_ddr_pll,
+};
+
+/* Calculates the rate for PLL divider.
  * If the divider value is not fixed then it gets the actual divider value
  * from divider table. Then, it calculate the clock rate by dividing the
  * parent rate with actual divider value.
@@ -1495,6 +1619,7 @@ static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr,
 	[GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,
 	[GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,
+	[GCC_APPS_CPU_PLLDIV_CLK] = &gcc_apps_cpu_plldiv_clk.cdiv.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
index cd0cd23..921565d 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -90,6 +90,7 @@
 #define GCC_FEPLL500_CLK				71
 #define GCC_FEPLL_WCSS2G_CLK				72
 #define GCC_FEPLL_WCSS5G_CLK				73
+#define GCC_APPS_CPU_PLLDIV_CLK				74
 
 #define WIFI0_CPU_INIT_RESET				0
 #define WIFI0_RADIO_SRIF_RESET				1
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 3/7] clk: qcom: ipq4019: Added the nodes for pcnoc

[Abhishek Sahu]

The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.

Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/clk/qcom/gcc-ipq4019.c               | 39 ++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |  1 +
 2 files changed, 40 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 74f7ba8..211c68c 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1550,6 +1550,43 @@ static struct clk_pll_div gcc_fepllwcss5g_clk = {
 	.div_table = fepllwcss_clk_div_table
 };
 
+static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = {
+	F(48000000,  P_XO,	 1, 0, 0),
+	F(100000000, P_FEPLL200, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = {
+	.cmd_rcgr = 0x21024,
+	.hid_width = 5,
+	.parent_map = gcc_xo_200_500_map,
+	.freq_tbl = ftbl_gcc_pcnoc_ahb_clk,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gcc_pcnoc_ahb_clk_src",
+		.parent_names = gcc_xo_200_500,
+		.num_parents = 3,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch pcnoc_clk_src = {
+	.halt_reg = 0x21030,
+	.clkr = {
+		.enable_reg = 0x21030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "pcnoc_clk_src",
+			.parent_names = (const char *[]){
+				"gcc_pcnoc_ahb_clk_src",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+			.flags = CLK_SET_RATE_PARENT |
+				CLK_IS_CRITICAL,
+		},
+	},
+};
+
 static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[AUDIO_CLK_SRC] = &audio_clk_src.clkr,
 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -1620,6 +1657,8 @@ static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,
 	[GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,
 	[GCC_APPS_CPU_PLLDIV_CLK] = &gcc_apps_cpu_plldiv_clk.cdiv.clkr,
+	[GCC_PCNOC_AHB_CLK_SRC] = &gcc_pcnoc_ahb_clk_src.clkr,
+	[GCC_PCNOC_AHB_CLK] = &pcnoc_clk_src.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
index 921565d..3b98498 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -91,6 +91,7 @@
 #define GCC_FEPLL_WCSS2G_CLK				72
 #define GCC_FEPLL_WCSS5G_CLK				73
 #define GCC_APPS_CPU_PLLDIV_CLK				74
+#define GCC_PCNOC_AHB_CLK_SRC				75
 
 #define WIFI0_CPU_INIT_RESET				0
 #define WIFI0_RADIO_SRIF_RESET				1
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 4/7] clk: qcom: ipq4019: Added all the frequencies for apps cpu

[Abhishek Sahu]

The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 211c68c..160e0cf 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -565,10 +565,20 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 };
 
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
-	F(48000000, P_XO,	   1, 0, 0),
+	F(48000000,  P_XO,         1, 0, 0),
 	F(200000000, P_FEPLL200,   1, 0, 0),
+	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
 	F(500000000, P_FEPLL500,   1, 0, 0),
+	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
 	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 4/7] clk: qcom: ipq4019: Added all the frequencies for apps cpu

[Stephen Boyd]

On 09/21, Abhishek Sahu wrote:
> The APPS CPU clock does not contain all the frequencies in its
> frequency table so this patch adds the same.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/clk/qcom/gcc-ipq4019.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
> index 211c68c..160e0cf 100644
> --- a/drivers/clk/qcom/gcc-ipq4019.c
> +++ b/drivers/clk/qcom/gcc-ipq4019.c
> @@ -565,10 +565,20 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
>  };
>  
>  static const struct freq_tbl ftbl_gcc_apps_clk[] = {
> -	F(48000000, P_XO,	   1, 0, 0),
> +	F(48000000,  P_XO,         1, 0, 0),
>  	F(200000000, P_FEPLL200,   1, 0, 0),
> +	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
>  	F(500000000, P_FEPLL500,   1, 0, 0),
> +	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
>  	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
>  	{ }
>  };

Can't we have the determine_rate callback know the speeds of the
"fixed" PLLs and use those first if the rate hits exactly? And
then if that doesn't happen go try ddrpllapps and set the rate on
it? I'm hoping we can get rid of this frequency table.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 4/7] clk: qcom: ipq4019: Added all the frequencies for apps cpu

[Abhishek Sahu]

On 2016-11-02 06:54, Stephen Boyd wrote:
> On 09/21, Abhishek Sahu wrote:
>> The APPS CPU clock does not contain all the frequencies in its
>> frequency table so this patch adds the same.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>  drivers/clk/qcom/gcc-ipq4019.c | 12 +++++++++++-
>>  1 file changed, 11 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/clk/qcom/gcc-ipq4019.c 
>> b/drivers/clk/qcom/gcc-ipq4019.c
>> index 211c68c..160e0cf 100644
>> --- a/drivers/clk/qcom/gcc-ipq4019.c
>> +++ b/drivers/clk/qcom/gcc-ipq4019.c
>> @@ -565,10 +565,20 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
>>  };
>> 
>>  static const struct freq_tbl ftbl_gcc_apps_clk[] = {
>> -	F(48000000, P_XO,	   1, 0, 0),
>> +	F(48000000,  P_XO,         1, 0, 0),
>>  	F(200000000, P_FEPLL200,   1, 0, 0),
>> +	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
>>  	F(500000000, P_FEPLL500,   1, 0, 0),
>> +	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
>>  	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
>> +	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
>>  	{ }
>>  };
> 
> Can't we have the determine_rate callback know the speeds of the
> "fixed" PLLs and use those first if the rate hits exactly? And
> then if that doesn't happen go try ddrpllapps and set the rate on
> it? I'm hoping we can get rid of this frequency table.
This clock is being registered with QCOM clk_rcg2 operations which
already has determine_rate callback based on this frequency table.
Currently all the frequencies are being generated without HID
divider but in future, we can have some frequency which will use
dividers also.
-- 
Abhishek Sahu

[PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name

[Abhishek Sahu]

1. The parent for sdcc clock is sdccpll so corrected the same
   in its parent map.
2. The frequency value was wrong so changed to correct
   frequency.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 160e0cf..b2decd5 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -120,7 +120,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
 
 static const char * const gcc_xo_sdcc1_500[] = {
 	"xo",
-	"ddrpll",
+	"ddrpllsdcc",
 	"fepll500",
 };
 
@@ -540,13 +540,13 @@ static struct clk_branch gcc_gp3_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
-	F(144000,    P_XO,			1,  3, 240),
-	F(400000,    P_XO,			1,  1, 0),
-	F(20000000,  P_FEPLL500,		1,  1, 25),
-	F(25000000,  P_FEPLL500,		1,  1, 20),
-	F(50000000,  P_FEPLL500,		1,  1, 10),
-	F(100000000, P_FEPLL500,		1,  1, 5),
-	F(193000000, P_DDRPLL,		1,  0, 0),
+	F(144000,    P_XO,       1,  3, 240),
+	F(400000,    P_XO,       1,  1, 0),
+	F(20000000,  P_FEPLL500, 1,  1, 25),
+	F(25000000,  P_FEPLL500, 1,  1, 20),
+	F(50000000,  P_FEPLL500, 1,  1, 10),
+	F(100000000, P_FEPLL500, 1,  1, 5),
+	F(190000000, P_DDRPLL,   1,  0, 0),
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name

[Stephen Boyd]

On 09/21, Abhishek Sahu wrote:
> 1. The parent for sdcc clock is sdccpll so corrected the same
>    in its parent map.
> 2. The frequency value was wrong so changed to correct
>    frequency.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/clk/qcom/gcc-ipq4019.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
> index 160e0cf..b2decd5 100644
> --- a/drivers/clk/qcom/gcc-ipq4019.c
> +++ b/drivers/clk/qcom/gcc-ipq4019.c
> @@ -120,7 +120,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
>  
>  static const char * const gcc_xo_sdcc1_500[] = {
>  	"xo",
> -	"ddrpll",
> +	"ddrpllsdcc",
>  	"fepll500",
>  };
>  
> @@ -540,13 +540,13 @@ static struct clk_branch gcc_gp3_clk = {
>  };
>  
>  static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
> -	F(144000,    P_XO,			1,  3, 240),
> -	F(400000,    P_XO,			1,  1, 0),
> -	F(20000000,  P_FEPLL500,		1,  1, 25),
> -	F(25000000,  P_FEPLL500,		1,  1, 20),
> -	F(50000000,  P_FEPLL500,		1,  1, 10),
> -	F(100000000, P_FEPLL500,		1,  1, 5),

None of these changed? Please leave them alone then.

> -	F(193000000, P_DDRPLL,		1,  0, 0),
> +	F(144000,    P_XO,       1,  3, 240),
> +	F(400000,    P_XO,       1,  1, 0),
> +	F(20000000,  P_FEPLL500, 1,  1, 25),
> +	F(25000000,  P_FEPLL500, 1,  1, 20),
> +	F(50000000,  P_FEPLL500, 1,  1, 10),
> +	F(100000000, P_FEPLL500, 1,  1, 5),
> +	F(190000000, P_DDRPLL,   1,  0, 0),

And tab out this one appropriately so that it lines up. Then the
diff is very clear.

>  	{ }

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll

[Abhishek Sahu]

The feedback divider for DDR PLL has been changed in IPQ4019
bootloader from 111 to 112 so changed the frequency values
for the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 52 +++++++++++++++++++++---------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index b2decd5..a2809db 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -546,7 +546,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
 	F(25000000,  P_FEPLL500, 1,  1, 20),
 	F(50000000,  P_FEPLL500, 1,  1, 10),
 	F(100000000, P_FEPLL500, 1,  1, 5),
-	F(190000000, P_DDRPLL,   1,  0, 0),
+	F(192000000, P_DDRPLL,   1,  0, 0),
 	{ }
 };
 
@@ -567,18 +567,18 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
 	F(48000000,  P_XO,         1, 0, 0),
 	F(200000000, P_FEPLL200,   1, 0, 0),
-	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(384000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(413000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(448000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(488000000, P_DDRPLLAPSS, 1, 0, 0),
 	F(500000000, P_FEPLL500,   1, 0, 0),
-	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(512000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(537000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(565000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(597000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(632000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(672000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(716000000, P_DDRPLLAPSS, 1, 0, 0),
 	{ }
 };
 
@@ -1381,20 +1381,20 @@ static const struct clk_ops clk_regmap_cpu_div_ops = {
 };
 
 static const struct freq_tbl ftbl_apps_ddr_pll[] = {
-	{ 380000000, P_XO, 0xd, 0, 0 },
-	{ 409000000, P_XO, 0xc, 0, 0 },
-	{ 444000000, P_XO, 0xb, 0, 0 },
-	{ 484000000, P_XO, 0xa, 0, 0 },
-	{ 507000000, P_XO, 0x9, 0, 0 },
-	{ 532000000, P_XO, 0x8, 0, 0 },
-	{ 560000000, P_XO, 0x7, 0, 0 },
-	{ 592000000, P_XO, 0x6, 0, 0 },
-	{ 626000000, P_XO, 0x5, 0, 0 },
-	{ 666000000, P_XO, 0x4, 0, 0 },
-	{ 710000000, P_XO, 0x3, 0, 0 },
-	{ 761000000, P_XO, 0x2, 0, 0 },
-	{ 819000000, P_XO, 0x1, 0, 0 },
-	{ 888000000, P_XO, 0x0, 0, 0 },
+	{ 384000000, P_XO, 0xd, 0, 0 },
+	{ 413000000, P_XO, 0xc, 0, 0 },
+	{ 448000000, P_XO, 0xb, 0, 0 },
+	{ 488000000, P_XO, 0xa, 0, 0 },
+	{ 512000000, P_XO, 0x9, 0, 0 },
+	{ 537000000, P_XO, 0x8, 0, 0 },
+	{ 565000000, P_XO, 0x7, 0, 0 },
+	{ 597000000, P_XO, 0x6, 0, 0 },
+	{ 632000000, P_XO, 0x5, 0, 0 },
+	{ 672000000, P_XO, 0x4, 0, 0 },
+	{ 716000000, P_XO, 0x3, 0, 0 },
+	{ 768000000, P_XO, 0x2, 0, 0 },
+	{ 823000000, P_XO, 0x1, 0, 0 },
+	{ 896000000, P_XO, 0x0, 0, 0 },
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll

[Stephen Boyd]

On 09/21, Abhishek Sahu wrote:
> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
> index b2decd5..a2809db 100644
> --- a/drivers/clk/qcom/gcc-ipq4019.c
> +++ b/drivers/clk/qcom/gcc-ipq4019.c
> @@ -546,7 +546,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
>  	F(25000000,  P_FEPLL500, 1,  1, 20),
>  	F(50000000,  P_FEPLL500, 1,  1, 10),
>  	F(100000000, P_FEPLL500, 1,  1, 5),
> -	F(190000000, P_DDRPLL,   1,  0, 0),
> +	F(192000000, P_DDRPLL,   1,  0, 0),

Change from 193 to 190 to 192.... please do it once.

>  	{ }
>  };
>  
> @@ -567,18 +567,18 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
>  static const struct freq_tbl ftbl_gcc_apps_clk[] = {
>  	F(48000000,  P_XO,         1, 0, 0),
>  	F(200000000, P_FEPLL200,   1, 0, 0),
> -	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(384000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(413000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(448000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(488000000, P_DDRPLLAPSS, 1, 0, 0),
>  	F(500000000, P_FEPLL500,   1, 0, 0),
> -	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(512000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(537000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(565000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(597000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(632000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(672000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(716000000, P_DDRPLLAPSS, 1, 0, 0),

Didn't this patch series introduce table updates already? Why
can't this patch be squashed with that one?

>  	{ }

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 7/7] clk: qcom: ipq4019: changed i2c freq table

[Abhishek Sahu]

The current I2C freq table uses MND values which is not
applicable for I2C since its RCG does not have MND
counter. This patch updates the freq table for 19.05
MHz clk frequency with FEPLL_200 parent.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index a2809db..314aa35 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -225,8 +225,7 @@ static struct clk_branch gcc_audio_pwm_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
-	F(19200000, P_XO, 1, 2, 5),
-	F(24000000, P_XO, 1, 1, 2),
+	F(19050000, P_FEPLL200, 10.5, 1, 1),
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 7/7] clk: qcom: ipq4019: changed i2c freq table

[Stephen Boyd]

On 09/21, Abhishek Sahu wrote:
> The current I2C freq table uses MND values which is not
> applicable for I2C since its RCG does not have MND
> counter. This patch updates the freq table for 19.05
> MHz clk frequency with FEPLL_200 parent.

That's concerning given that we read the registers, but I guess
it works out?

> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project