From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH 0/1] rnndb: a5xx: Update/enhance registers Date: Mon, 24 Oct 2016 10:29:34 -0600 Message-ID: <1477326575-7483-1-git-send-email-jcrouse@codeaurora.org> Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:33347 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965240AbcJXQ3s (ORCPT ); Mon, 24 Oct 2016 12:29:48 -0400 Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org Hi all. I know it is a bit fancy to send a cover email for a single but I thought some introductions were in order. This is the first of I hope many patches enhancing, improving and expanding Adreno support upstream including the brand spanking new Adreno A5XX family. I'll be available as much as possible to offer code and suggestions and take grievances. To start things off, this patch expands on the existing register database, fleshing out some of the bitfield definitions and adding a few new registers here and there. Best regards, Jordan