* [PATCH 0/1] rnndb: a5xx: Update/enhance registers @ 2016-10-24 16:29 Jordan Crouse 2016-10-24 16:29 ` [PATCH] " Jordan Crouse 0 siblings, 1 reply; 4+ messages in thread From: Jordan Crouse @ 2016-10-24 16:29 UTC (permalink / raw) To: freedreno; +Cc: linux-arm-msm Hi all. I know it is a bit fancy to send a cover email for a single but I thought some introductions were in order. This is the first of I hope many patches enhancing, improving and expanding Adreno support upstream including the brand spanking new Adreno A5XX family. I'll be available as much as possible to offer code and suggestions and take grievances. To start things off, this patch expands on the existing register database, fleshing out some of the bitfield definitions and adding a few new registers here and there. Best regards, Jordan ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] rnndb: a5xx: Update/enhance registers 2016-10-24 16:29 [PATCH 0/1] rnndb: a5xx: Update/enhance registers Jordan Crouse @ 2016-10-24 16:29 ` Jordan Crouse 2016-10-24 20:34 ` [Freedreno] " Rob Clark 0 siblings, 1 reply; 4+ messages in thread From: Jordan Crouse @ 2016-10-24 16:29 UTC (permalink / raw) To: freedreno; +Cc: linux-arm-msm Add some missing registers from downstream, rename a few to be more accurate and expand the bitfields for CP_INTERRUPT_STATUS, RBBM_STATUS and RBBM_INT0. --- rnndb/adreno/a5xx.xml | 109 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 91 insertions(+), 18 deletions(-) diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml index f7264a7..45c0f35 100644 --- a/rnndb/adreno/a5xx.xml +++ b/rnndb/adreno/a5xx.xml @@ -146,20 +146,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> </bitset> - <!-- CP Interrupt bits --> - <bitset name="A5XX_CP_INT"> - <bitfield name="CP_OPCODE_ERROR" pos="0"/> - <bitfield name="CP_RESERVED_BIT_ERROR" pos="1"/> - <bitfield name="CP_HW_FAULT_ERROR" pos="2"/> - <bitfield name="CP_DMA_ERROR" pos="3"/> - <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/> - <bitfield name="CP_AHB_ERROR" pos="5"/> - </bitset> - <!-- CP registers --> <reg32 offset="0x0800" name="CP_RB_BASE"/> <reg32 offset="0x0801" name="CP_RB_BASE_HI"/> <reg32 offset="0x0802" name="CP_RB_CNTL"/> + <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/> + <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/> <reg32 offset="0x0806" name="CP_RB_RPTR"/> <reg32 offset="0x0807" name="CP_RB_WPTR"/> <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/> @@ -186,12 +178,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/> <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/> <reg32 offset="0x0831" name="CP_CNTL"/> - <reg32 offset="0x0832" name="CP_ME_CNTL"/> + <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/> <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/> <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/> <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/> - <reg32 offset="0x0838" name="CP_PM4_INSTR_BASE_LO"/> - <reg32 offset="0x0839" name="CP_PM4_INSTR_BASE_HI"/> + <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/> + <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/> <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/> <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/> <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/> @@ -202,7 +194,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL"/> <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/> <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/> - <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/> + <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"> + <bitfield high="5" low="5" name="AHB_ERROR" /> + <bitfield high="4" low="4" name="REGISTER_PROTECTION" /> + <bitfield high="3" low="3" name="DMA_ERROR" /> + <bitfield high="2" low="2" name="CP_HW_FAULT" /> + <bitfield high="0" low="0" name="OPCODE_ERROR" /> + </reg32> <reg32 offset="0x0b1a" name="CP_HW_FAULT"/> <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/> <reg32 offset="0x0b1f" name="CP_IB1_BASE"/> @@ -211,7 +209,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0b22" name="CP_IB2_BASE"/> <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/> <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/> - <reg32 offset="0x0880" name="CP_PROTECT_REG_0"/> + <array offset="0x0b78" name="CP_SCRATCH_REG" stride="1" length="8"/> + <array offset="0x0880" name="CP_PROTECT" stride="1" length="32"> + <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/> + </array> <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/> <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/> <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0"/> @@ -271,7 +272,37 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/> <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/> - <reg32 offset="0x0038" name="RBBM_INT_0_MASK"/> + <reg32 offset="0x0038" name="RBBM_INT_0_MASK"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="RBBM_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/> + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> + <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/> + <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/> + <bitfield name="RBBM_GPC_ERROR" pos="7"/> + <bitfield name="CP_SW" pos="8"/> + <bitfield name="CP_HW_ERROR" pos="9"/> + <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/> + <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/> + <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/> + <bitfield name="CP_IB2" pos="13"/> + <bitfield name="CP_IB1" pos="14"/> + <bitfield name="CP_RB" pos="15"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_WT_DONE_TS" pos="18"/> + <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/> + <bitfield name="MISC_HANG_DETECT" pos="23"/> + <bitfield name="UCHE_OOB_ACCESS" pos="24"/> + <bitfield name="UCHE_TRAP_INTR" pos="25"/> + <bitfield name="DEBBUS_INTR_0" pos="26"/> + <bitfield name="DEBBUS_INTR_1" pos="27"/> + <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/> + <bitfield name="GPMU_FIRMWARE" pos="29"/> + <bitfield name="ISDB_CPU_IRQ" pos="30"/> + <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> + </reg32> <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/> <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/> <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/> @@ -590,11 +621,45 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3"/> <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/> <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/> - <reg32 offset="0x04f5" name="RBBM_STATUS"/> + <reg32 offset="0x04f5" name="RBBM_STATUS"> + <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" /> + <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" /> + <bitfield high="29" low="29" name="HLSQ_BUSY" /> + <bitfield high="28" low="28" name="VSC_BUSY" /> + <bitfield high="27" low="27" name="TPL1_BUSY" /> + <bitfield high="26" low="26" name="SP_BUSY" /> + <bitfield high="25" low="25" name="UCHE_BUSY" /> + <bitfield high="24" low="24" name="VPC_BUSY" /> + <bitfield high="23" low="23" name="VFDP_BUSY" /> + <bitfield high="22" low="22" name="VFD_BUSY" /> + <bitfield high="21" low="21" name="TESS_BUSY" /> + <bitfield high="20" low="20" name="PC_VSD_BUSY" /> + <bitfield high="19" low="19" name="PC_DCALL_BUSY" /> + <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" /> + <bitfield high="17" low="17" name="DCOM_BUSY" /> + <bitfield high="16" low="16" name="COM_BUSY" /> + <bitfield high="15" low="15" name="LRZ_BUZY" /> + <bitfield high="14" low="14" name="A2D_DSP_BUSY" /> + <bitfield high="13" low="13" name="CCUFCHE_BUSY" /> + <bitfield high="12" low="12" name="RB_BUSY" /> + <bitfield high="11" low="11" name="RAS_BUSY" /> + <bitfield high="10" low="10" name="TSE_BUSY" /> + <bitfield high="9" low="9" name="VBIF_BUSY" /> + <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" /> + <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" /> + <bitfield high="6" low="6" name="CP_BUSY" /> + <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" /> + <bitfield high="4" low="4" name="CP_CRASH_BUSY" /> + <bitfield high="3" low="3" name="CP_ETS_BUSY" /> + <bitfield high="2" low="2" name="CP_PFP_BUSY" /> + <bitfield high="1" low="1" name="CP_ME_BUSY" /> + <bitfield high="0" low="0" name="HI_BUSY" /> + </reg32> <reg32 offset="0x0530" name="RBBM_STATUS3"/> <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/> <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/> <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/> + <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/> <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/> <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/> <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/> @@ -730,7 +795,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/> <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/> <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/> - <reg32 offset="0x0e95" name="UCHE_INVALIDATE0"/> + <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/> + <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/> + <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/> + <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/> + <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/> + <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/> + <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/> <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/> <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0"/> <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1"/> @@ -744,6 +815,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/> <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/> <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/> + <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/> + <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/> <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/> <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL"/> -- 1.9.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Freedreno] [PATCH] rnndb: a5xx: Update/enhance registers 2016-10-24 16:29 ` [PATCH] " Jordan Crouse @ 2016-10-24 20:34 ` Rob Clark 0 siblings, 0 replies; 4+ messages in thread From: Rob Clark @ 2016-10-24 20:34 UTC (permalink / raw) To: Jordan Crouse; +Cc: freedreno, linux-arm-msm On Mon, Oct 24, 2016 at 12:29 PM, Jordan Crouse <jcrouse@codeaurora.org> wrote: > Add some missing registers from downstream, rename a few to be more > accurate and expand the bitfields for CP_INTERRUPT_STATUS, RBBM_STATUS > and RBBM_INT0. Hi Jordan, one small comment below > --- > rnndb/adreno/a5xx.xml | 109 +++++++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 91 insertions(+), 18 deletions(-) > > diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml > index f7264a7..45c0f35 100644 > --- a/rnndb/adreno/a5xx.xml > +++ b/rnndb/adreno/a5xx.xml > @@ -146,20 +146,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> > </bitset> > > - <!-- CP Interrupt bits --> > - <bitset name="A5XX_CP_INT"> > - <bitfield name="CP_OPCODE_ERROR" pos="0"/> > - <bitfield name="CP_RESERVED_BIT_ERROR" pos="1"/> > - <bitfield name="CP_HW_FAULT_ERROR" pos="2"/> > - <bitfield name="CP_DMA_ERROR" pos="3"/> > - <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/> > - <bitfield name="CP_AHB_ERROR" pos="5"/> > - </bitset> > - > <!-- CP registers --> > <reg32 offset="0x0800" name="CP_RB_BASE"/> > <reg32 offset="0x0801" name="CP_RB_BASE_HI"/> > <reg32 offset="0x0802" name="CP_RB_CNTL"/> > + <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/> > + <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/> > <reg32 offset="0x0806" name="CP_RB_RPTR"/> > <reg32 offset="0x0807" name="CP_RB_WPTR"/> > <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/> > @@ -186,12 +178,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/> > <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/> > <reg32 offset="0x0831" name="CP_CNTL"/> > - <reg32 offset="0x0832" name="CP_ME_CNTL"/> > + <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/> > <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/> > <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/> > <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/> > - <reg32 offset="0x0838" name="CP_PM4_INSTR_BASE_LO"/> > - <reg32 offset="0x0839" name="CP_PM4_INSTR_BASE_HI"/> > + <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/> > + <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/> > <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/> > <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/> > <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/> > @@ -202,7 +194,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL"/> > <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/> > <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/> > - <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/> > + <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"> > + <bitfield high="5" low="5" name="AHB_ERROR" /> > + <bitfield high="4" low="4" name="REGISTER_PROTECTION" /> > + <bitfield high="3" low="3" name="DMA_ERROR" /> > + <bitfield high="2" low="2" name="CP_HW_FAULT" /> > + <bitfield high="0" low="0" name="OPCODE_ERROR" /> fyi, when high==low you can just use pos="N" Also, you could just do: <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS" type="A5XX_CP_INT"/> (and not drop the earlier bitset) (tbh, I forgot why I split the irq bits out into a bitset for the earlier gen's.. in some cases there were separate enable/status/clear registers which needed the same bitset, but that might have been just on the mdp4/mdp5 side of things) BR, -R > + </reg32> > <reg32 offset="0x0b1a" name="CP_HW_FAULT"/> > <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/> > <reg32 offset="0x0b1f" name="CP_IB1_BASE"/> > @@ -211,7 +209,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x0b22" name="CP_IB2_BASE"/> > <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/> > <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/> > - <reg32 offset="0x0880" name="CP_PROTECT_REG_0"/> > + <array offset="0x0b78" name="CP_SCRATCH_REG" stride="1" length="8"/> > + <array offset="0x0880" name="CP_PROTECT" stride="1" length="32"> > + <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/> > + </array> > <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/> > <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/> > <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0"/> > @@ -271,7 +272,37 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/> > <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> > <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/> > - <reg32 offset="0x0038" name="RBBM_INT_0_MASK"/> > + <reg32 offset="0x0038" name="RBBM_INT_0_MASK"> > + <bitfield name="RBBM_GPU_IDLE" pos="0"/> > + <bitfield name="RBBM_AHB_ERROR" pos="1"/> > + <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/> > + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> > + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> > + <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/> > + <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/> > + <bitfield name="RBBM_GPC_ERROR" pos="7"/> > + <bitfield name="CP_SW" pos="8"/> > + <bitfield name="CP_HW_ERROR" pos="9"/> > + <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/> > + <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/> > + <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/> > + <bitfield name="CP_IB2" pos="13"/> > + <bitfield name="CP_IB1" pos="14"/> > + <bitfield name="CP_RB" pos="15"/> > + <bitfield name="CP_RB_DONE_TS" pos="17"/> > + <bitfield name="CP_WT_DONE_TS" pos="18"/> > + <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/> > + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/> > + <bitfield name="MISC_HANG_DETECT" pos="23"/> > + <bitfield name="UCHE_OOB_ACCESS" pos="24"/> > + <bitfield name="UCHE_TRAP_INTR" pos="25"/> > + <bitfield name="DEBBUS_INTR_0" pos="26"/> > + <bitfield name="DEBBUS_INTR_1" pos="27"/> > + <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/> > + <bitfield name="GPMU_FIRMWARE" pos="29"/> > + <bitfield name="ISDB_CPU_IRQ" pos="30"/> > + <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> > + </reg32> > <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/> > <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/> > <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/> > @@ -590,11 +621,45 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3"/> > <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/> > <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/> > - <reg32 offset="0x04f5" name="RBBM_STATUS"/> > + <reg32 offset="0x04f5" name="RBBM_STATUS"> > + <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" /> > + <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" /> > + <bitfield high="29" low="29" name="HLSQ_BUSY" /> > + <bitfield high="28" low="28" name="VSC_BUSY" /> > + <bitfield high="27" low="27" name="TPL1_BUSY" /> > + <bitfield high="26" low="26" name="SP_BUSY" /> > + <bitfield high="25" low="25" name="UCHE_BUSY" /> > + <bitfield high="24" low="24" name="VPC_BUSY" /> > + <bitfield high="23" low="23" name="VFDP_BUSY" /> > + <bitfield high="22" low="22" name="VFD_BUSY" /> > + <bitfield high="21" low="21" name="TESS_BUSY" /> > + <bitfield high="20" low="20" name="PC_VSD_BUSY" /> > + <bitfield high="19" low="19" name="PC_DCALL_BUSY" /> > + <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" /> > + <bitfield high="17" low="17" name="DCOM_BUSY" /> > + <bitfield high="16" low="16" name="COM_BUSY" /> > + <bitfield high="15" low="15" name="LRZ_BUZY" /> > + <bitfield high="14" low="14" name="A2D_DSP_BUSY" /> > + <bitfield high="13" low="13" name="CCUFCHE_BUSY" /> > + <bitfield high="12" low="12" name="RB_BUSY" /> > + <bitfield high="11" low="11" name="RAS_BUSY" /> > + <bitfield high="10" low="10" name="TSE_BUSY" /> > + <bitfield high="9" low="9" name="VBIF_BUSY" /> > + <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" /> > + <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" /> > + <bitfield high="6" low="6" name="CP_BUSY" /> > + <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" /> > + <bitfield high="4" low="4" name="CP_CRASH_BUSY" /> > + <bitfield high="3" low="3" name="CP_ETS_BUSY" /> > + <bitfield high="2" low="2" name="CP_PFP_BUSY" /> > + <bitfield high="1" low="1" name="CP_ME_BUSY" /> > + <bitfield high="0" low="0" name="HI_BUSY" /> > + </reg32> > <reg32 offset="0x0530" name="RBBM_STATUS3"/> > <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/> > <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/> > <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/> > + <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/> > <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/> > <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/> > <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/> > @@ -730,7 +795,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/> > <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/> > <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/> > - <reg32 offset="0x0e95" name="UCHE_INVALIDATE0"/> > + <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/> > + <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/> > + <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/> > + <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/> > + <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/> > + <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/> > + <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/> > <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/> > <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0"/> > <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1"/> > @@ -744,6 +815,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/> > <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/> > <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/> > + <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/> > + <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/> > > <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/> > <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL"/> > -- > 1.9.1 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno ^ permalink raw reply [flat|nested] 4+ messages in thread
* [v2 REALLY] rnndb: a5xx: Update/enhance registers
@ 2016-11-04 22:16 Jordan Crouse
[not found] ` <1478297767-5322-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Jordan Crouse @ 2016-11-04 22:16 UTC (permalink / raw)
To: freedreno; +Cc: linux-arm-msm
Update 5XX registers in the rnndb database ahead of 5XX support for DRM.
Changes:
v2: Make changes per Rob Clark.
Jordan
^ permalink raw reply [flat|nested] 4+ messages in thread[parent not found: <1478297767-5322-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]
* [PATCH] rnndb: a5xx: Update/enhance registers [not found] ` <1478297767-5322-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> @ 2016-11-04 22:16 ` Jordan Crouse 0 siblings, 0 replies; 4+ messages in thread From: Jordan Crouse @ 2016-11-04 22:16 UTC (permalink / raw) To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA Add some missing registers from downstream, rename a few to be more accurate and expand the bitfields for CP_INTERRUPT_STATUS, RBBM_STATUS and RBBM_INT0. --- rnndb/adreno/a5xx.xml | 80 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 75 insertions(+), 5 deletions(-) diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml index 706bbb2..17b3361 100644 --- a/rnndb/adreno/a5xx.xml +++ b/rnndb/adreno/a5xx.xml @@ -182,6 +182,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0800" name="CP_RB_BASE"/> <reg32 offset="0x0801" name="CP_RB_BASE_HI"/> <reg32 offset="0x0802" name="CP_RB_CNTL"/> + <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/> + <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/> <reg32 offset="0x0806" name="CP_RB_RPTR"/> <reg32 offset="0x0807" name="CP_RB_WPTR"/> <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/> @@ -208,12 +210,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/> <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/> <reg32 offset="0x0831" name="CP_CNTL"/> - <reg32 offset="0x0832" name="CP_ME_CNTL"/> + <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/> <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/> <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/> <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/> - <reg32 offset="0x0838" name="CP_PM4_INSTR_BASE_LO"/> - <reg32 offset="0x0839" name="CP_PM4_INSTR_BASE_HI"/> + <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/> + <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/> <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/> <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/> <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/> @@ -298,7 +300,37 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/> <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/> - <reg32 offset="0x0038" name="RBBM_INT_0_MASK"/> + <reg32 offset="0x0038" name="RBBM_INT_0_MASK"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="RBBM_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/> + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> + <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/> + <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/> + <bitfield name="RBBM_GPC_ERROR" pos="7"/> + <bitfield name="CP_SW" pos="8"/> + <bitfield name="CP_HW_ERROR" pos="9"/> + <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/> + <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/> + <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/> + <bitfield name="CP_IB2" pos="13"/> + <bitfield name="CP_IB1" pos="14"/> + <bitfield name="CP_RB" pos="15"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_WT_DONE_TS" pos="18"/> + <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/> + <bitfield name="MISC_HANG_DETECT" pos="23"/> + <bitfield name="UCHE_OOB_ACCESS" pos="24"/> + <bitfield name="UCHE_TRAP_INTR" pos="25"/> + <bitfield name="DEBBUS_INTR_0" pos="26"/> + <bitfield name="DEBBUS_INTR_1" pos="27"/> + <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/> + <bitfield name="GPMU_FIRMWARE" pos="29"/> + <bitfield name="ISDB_CPU_IRQ" pos="30"/> + <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> + </reg32> <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/> <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/> <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/> @@ -617,11 +649,45 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3"/> <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/> <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/> - <reg32 offset="0x04f5" name="RBBM_STATUS"/> + <reg32 offset="0x04f5" name="RBBM_STATUS"> + <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" /> + <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" /> + <bitfield high="29" low="29" name="HLSQ_BUSY" /> + <bitfield high="28" low="28" name="VSC_BUSY" /> + <bitfield high="27" low="27" name="TPL1_BUSY" /> + <bitfield high="26" low="26" name="SP_BUSY" /> + <bitfield high="25" low="25" name="UCHE_BUSY" /> + <bitfield high="24" low="24" name="VPC_BUSY" /> + <bitfield high="23" low="23" name="VFDP_BUSY" /> + <bitfield high="22" low="22" name="VFD_BUSY" /> + <bitfield high="21" low="21" name="TESS_BUSY" /> + <bitfield high="20" low="20" name="PC_VSD_BUSY" /> + <bitfield high="19" low="19" name="PC_DCALL_BUSY" /> + <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" /> + <bitfield high="17" low="17" name="DCOM_BUSY" /> + <bitfield high="16" low="16" name="COM_BUSY" /> + <bitfield high="15" low="15" name="LRZ_BUZY" /> + <bitfield high="14" low="14" name="A2D_DSP_BUSY" /> + <bitfield high="13" low="13" name="CCUFCHE_BUSY" /> + <bitfield high="12" low="12" name="RB_BUSY" /> + <bitfield high="11" low="11" name="RAS_BUSY" /> + <bitfield high="10" low="10" name="TSE_BUSY" /> + <bitfield high="9" low="9" name="VBIF_BUSY" /> + <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" /> + <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" /> + <bitfield high="6" low="6" name="CP_BUSY" /> + <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" /> + <bitfield high="4" low="4" name="CP_CRASH_BUSY" /> + <bitfield high="3" low="3" name="CP_ETS_BUSY" /> + <bitfield high="2" low="2" name="CP_PFP_BUSY" /> + <bitfield high="1" low="1" name="CP_ME_BUSY" /> + <bitfield high="0" low="0" name="HI_BUSY" /> + </reg32> <reg32 offset="0x0530" name="RBBM_STATUS3"/> <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/> <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/> <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/> + <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/> <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/> <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/> <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/> @@ -772,6 +838,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/> <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/> <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/> + <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/> + <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/> <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/> <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/> <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/> @@ -790,6 +858,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/> <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/> <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/> + <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/> + <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/> <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/> <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL"/> -- 1.9.1 _______________________________________________ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno ^ permalink raw reply related [flat|nested] 4+ messages in thread
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2016-10-24 16:29 [PATCH 0/1] rnndb: a5xx: Update/enhance registers Jordan Crouse
2016-10-24 16:29 ` [PATCH] " Jordan Crouse
2016-10-24 20:34 ` [Freedreno] " Rob Clark
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2016-11-04 22:16 [v2 REALLY] " Jordan Crouse
[not found] ` <1478297767-5322-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-04 22:16 ` [PATCH] " Jordan Crouse
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