* [v2] rnndb: a5xx: Update/enhance registers
@ 2016-11-04 22:10 Jordan Crouse
2016-11-04 22:10 ` [PATCH] rnndb: a5xx: Add A540 registers Jordan Crouse
0 siblings, 1 reply; 3+ messages in thread
From: Jordan Crouse @ 2016-11-04 22:10 UTC (permalink / raw)
To: freedreno; +Cc: linux-arm-msm
Updated version of the a5xx registers. Changelog:
v2: Remove CP_INTERRUPT_STATUS bitfield per Rob Clark
Jordan
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] rnndb: a5xx: Add A540 registers
2016-11-04 22:10 [v2] rnndb: a5xx: Update/enhance registers Jordan Crouse
@ 2016-11-04 22:10 ` Jordan Crouse
2016-11-04 22:12 ` [Freedreno] " Jordan Crouse
0 siblings, 1 reply; 3+ messages in thread
From: Jordan Crouse @ 2016-11-04 22:10 UTC (permalink / raw)
To: freedreno; +Cc: linux-arm-msm
Flesh out a few of the GPMU registers for A540.
---
rnndb/adreno/a5xx.xml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml
index 17b3361..6e43330 100644
--- a/rnndb/adreno/a5xx.xml
+++ b/rnndb/adreno/a5xx.xml
@@ -1050,7 +1050,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
<reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
<reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
- <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
+ <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG">
+ <bitfield high="3" low="0" name="ISENSE_STATUS"/>
+ <bitfield pos="1" name="BCL_ENABLED"/>
+ <bitfield pos="9" name="LLM_ENABLED"/>
+ </reg32>
<reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
<reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
<reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
@@ -1064,8 +1068,14 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
<reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
<reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
- <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
- <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
+ <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL">
+ <bitfield pos="0" name="IDLE_FULL_LM"/>
+ <bitfield high="5" low="4" name="STATE_OF_CHILD"/>
+ </reg32>
+ <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS">
+ <bitfield pos="0" name="IDLE_FULL_ACK"/>
+ <bitfield pos="1" name="WAKEUP_ACK"/>
+ </reg32>
<reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
<reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
<reg32 offset="0xb80f" name="GDPM_INT_EN"/>
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Freedreno] [PATCH] rnndb: a5xx: Add A540 registers
2016-11-04 22:10 ` [PATCH] rnndb: a5xx: Add A540 registers Jordan Crouse
@ 2016-11-04 22:12 ` Jordan Crouse
0 siblings, 0 replies; 3+ messages in thread
From: Jordan Crouse @ 2016-11-04 22:12 UTC (permalink / raw)
To: freedreno; +Cc: linux-arm-msm
On Fri, Nov 04, 2016 at 04:10:15PM -0600, Jordan Crouse wrote:
> Flesh out a few of the GPMU registers for A540.
> ---
> rnndb/adreno/a5xx.xml | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml
> index 17b3361..6e43330 100644
> --- a/rnndb/adreno/a5xx.xml
> +++ b/rnndb/adreno/a5xx.xml
> @@ -1050,7 +1050,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
> <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
> <reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
> <reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
> - <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
> + <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG">
> + <bitfield high="3" low="0" name="ISENSE_STATUS"/>
> + <bitfield pos="1" name="BCL_ENABLED"/>
> + <bitfield pos="9" name="LLM_ENABLED"/>
> + </reg32>
> <reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
> <reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
> <reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
> @@ -1064,8 +1068,14 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
> <reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
> <reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
> <reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
> - <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
> - <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
> + <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL">
> + <bitfield pos="0" name="IDLE_FULL_LM"/>
> + <bitfield high="5" low="4" name="STATE_OF_CHILD"/>
> + </reg32>
> + <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS">
> + <bitfield pos="0" name="IDLE_FULL_ACK"/>
> + <bitfield pos="1" name="WAKEUP_ACK"/>
> + </reg32>
> <reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
> <reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
> <reg32 offset="0xb80f" name="GDPM_INT_EN"/>
> --
> 1.9.1
Grumble - that was the wrong patch. Lets try that again with less foolishness.
Jordan
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-11-04 22:10 [v2] rnndb: a5xx: Update/enhance registers Jordan Crouse
2016-11-04 22:10 ` [PATCH] rnndb: a5xx: Add A540 registers Jordan Crouse
2016-11-04 22:12 ` [Freedreno] " Jordan Crouse
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