* [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions
@ 2016-12-02 15:30 Jordan Crouse
2016-12-02 18:30 ` Stephen Boyd
0 siblings, 1 reply; 5+ messages in thread
From: Jordan Crouse @ 2016-12-02 15:30 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 +++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index a3a4dee..4108f21 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -473,6 +473,84 @@
};
};
+ adreno_smmu: arm,smmu@b40000 {
+ compatible = "arm,smmu-v2";
+ reg = <0xb40000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <0 334 0>,
+ <0 329 0>,
+ <0 330 0>;
+ #iommu-cells = <1>;
+
+ clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
+ <&mmcc MMSS_MMAGIC_CFG_AHB_CLK>,
+ <&mmcc GPU_AHB_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>;
+ clock-names = "mmagic_ahb_clk",
+ "mmagic_cfg_ahb_clk",
+ "gpu_ahb_clk",
+ "gcc_mmss_bimc_gfx_clk",
+ "gcc_bimc_gfx_clk",
+ "mmss_misc_bus_clk";
+
+ power-domains = <&mmcc GPU_GDSC>;
+
+ qcom,skip-init;
+ qcom,register-save;
+
+ status = "okay";
+ };
+
+ adreno-3xx@b00000 {
+ compatible = "qcom,adreno-3xx";
+ #stream-id-cells = <16>;
+
+ reg = <0xb00000 0x3f000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <0 300 0>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+ <&mmcc GPU_AHB_CLK>,
+ <&mmcc GPU_GX_RBBMTIMER_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&mmcc MMSS_MMAGIC_AHB_CLK>;
+
+ clock-names = "core_clk",
+ "iface_clk",
+ "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "alt_mem_iface_clk";
+
+ power-domains = <&mmcc GPU_GDSC>;
+ iommus = <&adreno_smmu 0>;
+
+ /* There are patchlevel 3 chips in the world (Snapdragon
+ * (820) but they are functionally similar to the 821 in
+ * the code so we can safely set the chipset as
+ * patchlevel 4. */
+ qcom,chipid = <0x05030004>;
+
+ /* This is a safe speed for bring up in all bin levels.
+ * This isn't the fastest the chip can go, but we can
+ * get there eventually */
+ qcom,gpu-pwrlevels {
+ compatible = "qcom,gpu-pwrlevels";
+ qcom,gpu-pwrlevel@0 {
+ qcom,gpu-freq = <205000000>;
+ };
+ qcom,gpu-pwrlevel@1 {
+ qcom,gpu-freq = <27000000>;
+ };
+ };
+ };
+
mdp_smmu: arm,smmu@d00000 {
compatible = "arm,smmu-v2";
reg = <0xd00000 0x10000>;
--
1.9.1
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions
2016-12-02 15:30 [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions Jordan Crouse
@ 2016-12-02 18:30 ` Stephen Boyd
0 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2016-12-02 18:30 UTC (permalink / raw)
To: Jordan Crouse, freedreno; +Cc: linux-arm-msm
On 12/02/2016 07:30 AM, Jordan Crouse wrote:
> Add an initial node for the Adreno GPU and it's companion
> SMMU. The GPU node is mostly complete except for a bare
> bones power table that will be filled out more completely
> later.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
Hm.. I see that I missed the 8064 dts update and Andy has already
applied it. Sigh.
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 +++++++++++++++++++++++++++++++++++
> 1 file changed, 78 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index a3a4dee..4108f21 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -473,6 +473,84 @@
> };
> };
>
> + adreno_smmu: arm,smmu@b40000 {
iommu@b40000 ?
> + compatible = "arm,smmu-v2";
> + reg = <0xb40000 0x10000>;
> +
> + #global-interrupts = <1>;
> + interrupts = <0 334 0>,
> + <0 329 0>,
> + <0 330 0>;
We're using the pretty macros now for GIC_SPI and irq triggers. Please
add them on interrupts.
> + #iommu-cells = <1>;
> +
> + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
> + <&mmcc MMSS_MMAGIC_CFG_AHB_CLK>,
> + <&mmcc GPU_AHB_CLK>,
> + <&gcc GCC_MMSS_BIMC_GFX_CLK>,
> + <&gcc GCC_BIMC_GFX_CLK>,
> + <&mmcc MMSS_MISC_AHB_CLK>;
> + clock-names = "mmagic_ahb_clk",
> + "mmagic_cfg_ahb_clk",
> + "gpu_ahb_clk",
> + "gcc_mmss_bimc_gfx_clk",
> + "gcc_bimc_gfx_clk",
> + "mmss_misc_bus_clk";
Please remove _clk from all clock names as it's redundant.
> +
> + power-domains = <&mmcc GPU_GDSC>;
> +
> + qcom,skip-init;
> + qcom,register-save;
> +
> + status = "okay";
We don't need status = "okay" here. Typically those are just in the
board files.
> + };
> +
> + adreno-3xx@b00000 {
gpu@b00000 ?
> + compatible = "qcom,adreno-3xx";
> + #stream-id-cells = <16>;
> +
> + reg = <0xb00000 0x3f000>;
> + reg-names = "kgsl_3d0_reg_memory";
> +
> + interrupts = <0 300 0>;
> + interrupt-names = "kgsl_3d0_irq";
> +
> + clocks = <&mmcc GPU_GX_GFX3D_CLK>,
> + <&mmcc GPU_AHB_CLK>,
> + <&mmcc GPU_GX_RBBMTIMER_CLK>,
> + <&gcc GCC_BIMC_GFX_CLK>,
> + <&gcc GCC_MMSS_BIMC_GFX_CLK>,
> + <&mmcc MMSS_MMAGIC_AHB_CLK>;
> +
> + clock-names = "core_clk",
> + "iface_clk",
> + "rbbmtimer_clk",
> + "mem_clk",
> + "mem_iface_clk",
> + "alt_mem_iface_clk";
Is there a binding update for new clock names? I haven't seen it. Sad
that we couldn't remove _clk from the names here like everywhere else.
> +
> + power-domains = <&mmcc GPU_GDSC>;
> + iommus = <&adreno_smmu 0>;
> +
> + /* There are patchlevel 3 chips in the world (Snapdragon
> + * (820) but they are functionally similar to the 821 in
> + * the code so we can safely set the chipset as
> + * patchlevel 4. */
> + qcom,chipid = <0x05030004>;
> +
> + /* This is a safe speed for bring up in all bin levels.
> + * This isn't the fastest the chip can go, but we can
> + * get there eventually */
> + qcom,gpu-pwrlevels {
> + compatible = "qcom,gpu-pwrlevels";
> + qcom,gpu-pwrlevel@0 {
> + qcom,gpu-freq = <205000000>;
> + };
> + qcom,gpu-pwrlevel@1 {
> + qcom,gpu-freq = <27000000>;
> + };
> + };
These should be OPPs.
> + };
> +
> mdp_smmu: arm,smmu@d00000 {
> compatible = "arm,smmu-v2";
> reg = <0xd00000 0x10000>;
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions
@ 2019-01-29 13:23 Srinivas Kandagatla
2019-01-29 23:58 ` [PATCH] " Jordan Crouse
0 siblings, 1 reply; 5+ messages in thread
From: Srinivas Kandagatla @ 2019-01-29 13:23 UTC (permalink / raw)
To: andy.gross
Cc: devicetree, linux-arm-msm, Jordan Crouse, Srinivas Kandagatla,
Vivek Gautam, linux-arm-kernel
From: Jordan Crouse <jcrouse@codeaurora.org>
Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
[Remove mmagic clocks from GPU/smmu nodes]
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0d0b9482aa4d..b5f23594905c 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -84,6 +84,12 @@
qcom,client-id = <1>;
qcom,vmid = <15>;
};
+
+ zap_shader_region: gpu@8f200000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90b00000 0x0 0xa00000>;
+ no-map;
+ };
};
cpus {
@@ -1338,6 +1344,52 @@
};
};
+ gpu@b00000 {
+ compatible = "qcom,adreno-530.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0xb00000 0x3f000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+ <&mmcc GPU_AHB_CLK>,
+ <&mmcc GPU_GX_RBBMTIMER_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+ clock-names = "core",
+ "iface",
+ "rbbmtimer",
+ "mem",
+ "mem_iface";
+
+ power-domains = <&mmcc GPU_GDSC>;
+ iommus = <&adreno_smmu 0>;
+
+ qcom,gpu-quirk-two-pass-use-wfi;
+ qcom,gpu-quirk-fault-detect-mask;
+
+ /* This is a safe speed for bring up in all bin levels.
+ * This isn't the fastest the chip can go, but we can
+ * get there eventually */
+ qcom,gpu-pwrlevels {
+ compatible = "qcom,gpu-pwrlevels";
+ qcom,gpu-pwrlevel@0 {
+ qcom,gpu-freq = <510000000>;
+ };
+ qcom,gpu-pwrlevel@1 {
+ qcom,gpu-freq = <27000000>;
+ };
+ };
+
+ zap-shader {
+ memory-region = <&zap_shader_region>;
+ };
+ };
+
mdss: mdss@900000 {
compatible = "qcom,mdss";
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions
2019-01-29 13:23 [PATCH 4/6] " Srinivas Kandagatla
@ 2019-01-29 23:58 ` Jordan Crouse
2019-01-30 5:32 ` Vivek Gautam
0 siblings, 1 reply; 5+ messages in thread
From: Jordan Crouse @ 2019-01-29 23:58 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: andy.gross, linux-arm-msm, vivek.gautam, linux-arm-kernel,
devicetree
Add an initial node for the Adreno GPU and it's companion
SMMU.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
This is slightly updated version of [1] to include a correct OPP table and other
such stuff. I didn't know the best way to send it, so I attached it to the
original email and hopefully Andy forgives me. Otherwise, Srinivas can resend
it correctly.
[1] https://patchwork.kernel.org/patch/10786185/
arch/arm64/boot/dts/qcom/msm8996.dtsi | 86 +++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0d0b948..0950415 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -84,6 +84,12 @@
qcom,client-id = <1>;
qcom,vmid = <15>;
};
+
+ zap_shader_region: gpu@8f200000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90b00000 0x0 0xa00000>;
+ no-map;
+ };
};
cpus {
@@ -796,6 +802,11 @@
reg = <0x24f 0x1>;
bits = <1 4>;
};
+
+ gpu_speed_bin: gpu_speed_bin@133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
+ };
};
phy@34000 {
@@ -1338,6 +1349,81 @@
};
};
+ gpu@b00000 {
+ compatible = "qcom,adreno-530.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0xb00000 0x3f000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+ <&mmcc GPU_AHB_CLK>,
+ <&mmcc GPU_GX_RBBMTIMER_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+ clock-names = "core",
+ "iface",
+ "rbbmtimer",
+ "mem",
+ "mem_iface";
+
+ power-domains = <&mmcc GPU_GDSC>;
+ iommus = <&adreno_smmu 0>;
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
+ qcom,gpu-quirk-two-pass-use-wfi;
+ qcom,gpu-quirk-fault-detect-mask;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp-table {
+ compatible ="operating-points-v2";
+
+ /*
+ * 624Mhz and 560Mhz are only available on speed
+ * bin (1 << 0). All the rest are available on
+ * all bins of the hardware
+ */
+ opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-supported-hw = <0x01>;
+ };
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ opp-supported-hw = <0x01>;
+ };
+ opp-510000000 {
+ opp-hz = /bits/ 64 <510000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-401800000 {
+ opp-hz = /bits/ 64 <401800000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-214000000 {
+ opp-hz = /bits/ 64 <214000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-133000000 {
+ opp-hz = /bits/ 64 <133000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ };
+
+ zap-shader {
+ memory-region = <&zap_shader_region>;
+ };
+ };
+
mdss: mdss@900000 {
compatible = "qcom,mdss";
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions
2019-01-29 23:58 ` [PATCH] " Jordan Crouse
@ 2019-01-30 5:32 ` Vivek Gautam
2019-01-30 10:54 ` Srinivas Kandagatla
0 siblings, 1 reply; 5+ messages in thread
From: Vivek Gautam @ 2019-01-30 5:32 UTC (permalink / raw)
To: Jordan Crouse
Cc: Andy Gross, linux-arm-msm, Srinivas Kandagatla, Linux ARM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
Hi,
On Wed, Jan 30, 2019 at 5:29 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Add an initial node for the Adreno GPU and it's companion
> SMMU.
The SMMU node is in another patch, so may be change the title of this
patch and update the commit text too?
>
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
[snip]
Regards
Vivek
Vivek
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions
2019-01-30 5:32 ` Vivek Gautam
@ 2019-01-30 10:54 ` Srinivas Kandagatla
0 siblings, 0 replies; 5+ messages in thread
From: Srinivas Kandagatla @ 2019-01-30 10:54 UTC (permalink / raw)
To: Vivek Gautam, Jordan Crouse
Cc: Andy Gross, linux-arm-msm, Linux ARM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
Thanks Vivek,
On 30/01/2019 05:32, Vivek Gautam wrote:
> Hi,
>
> On Wed, Jan 30, 2019 at 5:29 AM Jordan Crouse<jcrouse@codeaurora.org> wrote:
>> Add an initial node for the Adreno GPU and it's companion
>> SMMU.
> The SMMU node is in another patch, so may be change the title of this
> patch and update the commit text too?
>
I will update this and send v2 of the series!
--srini
^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-12-02 18:30 ` Stephen Boyd
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2019-01-29 13:23 [PATCH 4/6] " Srinivas Kandagatla
2019-01-29 23:58 ` [PATCH] " Jordan Crouse
2019-01-30 5:32 ` Vivek Gautam
2019-01-30 10:54 ` Srinivas Kandagatla
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