[PATCH RFC 0/2] mmc: sdhci-msm: Configuring IO_PAD support for sdhci-msm

[PATCH RFC 0/2] mmc: sdhci-msm: Configuring IO_PAD support for sdhci-msm

[Vijay Viswanath]

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>From the HPG:
In some platform, SDCC controller can be connected to either an eMMC device or
an SD card. The PADs for SD card are dual-voltage that support 3v/1.8v. Those
PADs have a control signal  (io_pad_pwr_switch/mode18 ) that indicates whether
the PAD works in 3v or 1.8v.

For SD usage the default value of this signal is ‘0’, and SD driver changes it
to ‘1’ as a part of voltage switching sequence.
For eMMC usage, SW should configure this signal to ‘1’ and supply 1.8v to PADs
before starting any activity on the eMMC BUS.

To set this signal, write the following in the
SDC1_SDCC_HC_VENDOR_SPECIFIC_FUNC register:
	HC_IO_PAD_PWR_SWITCH: bit 16
	HC_IO_PAD_PWR_SWITCH_EN: bit 15

Krishna Konda (1):
  mmc: sdhci-msm: support voltage pad switching

Vijay Viswanath (1):
  mmc: sdhci-msm: Add support to store supported vdd-io voltages

 drivers/mmc/host/sdhci-msm.c | 76 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

-- 
 Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH RFC 1/2] mmc: sdhci-msm: Add support to store supported vdd-io voltages

[Vijay Viswanath]

During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.

Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index c283291..5c23e92 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -23,6 +23,7 @@
 #include <linux/iopoll.h>
 
 #include "sdhci-pltfm.h"
+#include <linux/regulator/consumer.h>
 
 #define CORE_MCI_VERSION		0x50
 #define CORE_VERSION_MAJOR_SHIFT	28
@@ -81,6 +82,9 @@
 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
+#define CORE_3_0V_SUPPORT	(1 << 25)
+#define CORE_1_8V_SUPPORT	(1 << 26)
+
 #define CORE_CSR_CDC_CTLR_CFG0		0x130
 #define CORE_SW_TRIG_FULL_CALIB		BIT(16)
 #define CORE_HW_AUTOCAL_ENA		BIT(17)
@@ -148,6 +152,7 @@ struct sdhci_msm_host {
 	u32 curr_io_level;
 	wait_queue_head_t pwr_irq_wait;
 	bool pwr_irq_flag;
+	u32 caps_0;
 };
 
 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
@@ -1313,6 +1318,35 @@ static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
 		sdhci_msm_check_power_status(host, req_type);
 }
 
+static int sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
+{
+	struct mmc_host *mmc = msm_host->mmc;
+	struct regulator *supply = mmc->supply.vqmmc;
+	int i, count;
+	u32 caps = 0, vdd_uV;
+
+	if (!IS_ERR(mmc->supply.vqmmc)) {
+		count = regulator_count_voltages(supply);
+		if (count < 0)
+			return count;
+		for (i = 0; i < count; i++) {
+			vdd_uV = regulator_list_voltage(supply, i);
+			if (vdd_uV <= 0)
+				continue;
+			if (vdd_uV > 2700000)
+				caps |= CORE_3_0V_SUPPORT;
+			if (vdd_uV < 1950000)
+				caps |= CORE_1_8V_SUPPORT;
+		}
+	}
+	msm_host->caps_0 |= caps;
+	pr_debug("%s: %s: supported caps: 0x%08x\n", mmc_hostname(mmc),
+			__func__, caps);
+
+	return 0;
+}
+
+
 static const struct of_device_id sdhci_msm_dt_match[] = {
 	{ .compatible = "qcom,sdhci-msm-v4" },
 	{},
@@ -1530,6 +1564,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 	ret = sdhci_add_host(host);
 	if (ret)
 		goto pm_runtime_disable;
+	ret = sdhci_msm_set_regulator_caps(msm_host);
+	if (ret)
+		dev_err(&pdev->dev, "%s: Failed to set regulator caps: %d\n",
+				__func__, ret);
 
 	pm_runtime_mark_last_busy(&pdev->dev);
 	pm_runtime_put_autosuspend(&pdev->dev);
-- 
 Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH RFC 1/2] mmc: sdhci-msm: Add support to store supported vdd-io voltages

[Adrian Hunter]

On 18/01/18 10:05, Vijay Viswanath wrote:
> During probe check whether the vdd-io regulator of sdhc platform device
> can support 1.8V and 3V and store this information as a capability of
> platform device.
> 
> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>

Not sure why this is RFC, but for sdhci:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index c283291..5c23e92 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -23,6 +23,7 @@
>  #include <linux/iopoll.h>
>  
>  #include "sdhci-pltfm.h"
> +#include <linux/regulator/consumer.h>
>  
>  #define CORE_MCI_VERSION		0x50
>  #define CORE_VERSION_MAJOR_SHIFT	28
> @@ -81,6 +82,9 @@
>  #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>  #define CORE_HC_SELECT_IN_MASK	(7 << 19)
>  
> +#define CORE_3_0V_SUPPORT	(1 << 25)
> +#define CORE_1_8V_SUPPORT	(1 << 26)
> +
>  #define CORE_CSR_CDC_CTLR_CFG0		0x130
>  #define CORE_SW_TRIG_FULL_CALIB		BIT(16)
>  #define CORE_HW_AUTOCAL_ENA		BIT(17)
> @@ -148,6 +152,7 @@ struct sdhci_msm_host {
>  	u32 curr_io_level;
>  	wait_queue_head_t pwr_irq_wait;
>  	bool pwr_irq_flag;
> +	u32 caps_0;
>  };
>  
>  static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
> @@ -1313,6 +1318,35 @@ static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
>  		sdhci_msm_check_power_status(host, req_type);
>  }
>  
> +static int sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
> +{
> +	struct mmc_host *mmc = msm_host->mmc;
> +	struct regulator *supply = mmc->supply.vqmmc;
> +	int i, count;
> +	u32 caps = 0, vdd_uV;
> +
> +	if (!IS_ERR(mmc->supply.vqmmc)) {
> +		count = regulator_count_voltages(supply);
> +		if (count < 0)
> +			return count;
> +		for (i = 0; i < count; i++) {
> +			vdd_uV = regulator_list_voltage(supply, i);
> +			if (vdd_uV <= 0)
> +				continue;
> +			if (vdd_uV > 2700000)
> +				caps |= CORE_3_0V_SUPPORT;
> +			if (vdd_uV < 1950000)
> +				caps |= CORE_1_8V_SUPPORT;
> +		}
> +	}
> +	msm_host->caps_0 |= caps;
> +	pr_debug("%s: %s: supported caps: 0x%08x\n", mmc_hostname(mmc),
> +			__func__, caps);
> +
> +	return 0;
> +}
> +
> +
>  static const struct of_device_id sdhci_msm_dt_match[] = {
>  	{ .compatible = "qcom,sdhci-msm-v4" },
>  	{},
> @@ -1530,6 +1564,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>  	ret = sdhci_add_host(host);
>  	if (ret)
>  		goto pm_runtime_disable;
> +	ret = sdhci_msm_set_regulator_caps(msm_host);
> +	if (ret)
> +		dev_err(&pdev->dev, "%s: Failed to set regulator caps: %d\n",
> +				__func__, ret);
>  
>  	pm_runtime_mark_last_busy(&pdev->dev);
>  	pm_runtime_put_autosuspend(&pdev->dev);
> 

[PATCH RFC 2/2] mmc: sdhci-msm: support voltage pad switching

[Vijay Viswanath]

From: Krishna Konda <kkonda@codeaurora.org>

The PADs for sdhc controller are dual-voltage that support 3v/1.8v.
Those PADs have a control signal (io_pad_pwr_switch/mode18 ) that
indicates whether the PAD works in 3v or 1.8v.

SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
based on actual voltage used for IO lines. So when power irq is
triggered for io high or io low, the driver should check the voltages
supported and set the pad accordingly.

Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 5c23e92..f5728a8 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -78,6 +78,8 @@
 #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
 #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
 #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
+#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
+#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
 #define CORE_HC_SELECT_IN_EN	BIT(18)
 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
@@ -1166,6 +1168,35 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
 	 */
 	writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
 
+	/*
+	 * SDHC has core_mem and hc_mem device memory and these memory
+	 * addresses do not fall within 1KB region. Hence, any update to
+	 * core_mem address space would require an mb() to ensure this gets
+	 * completed before its next update to registers within hc_mem.
+	 */
+	mb();
+	/*
+	 * We should unset IO PAD PWR switch only if the register write can
+	 * set IO lines high and the regulator also switches to 3 V.
+	 * Else, we should keep the IO PAD PWR switch set.
+	 * This is applicable to certain targets where eMMC vccq supply is only
+	 * 1.8V. In such targets, even during REQ_IO_HIGH, the IO PAD PWR
+	 * switch must be kept set to reflect actual regulator voltage. This
+	 * way, during initialization of controllers with only 1.8V, we will
+	 * set the IO PAD bit without waiting for a REQ_IO_LOW.
+	 */
+	if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT))
+		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
+					~CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
+				CORE_VENDOR_SPEC);
+	else if ((io_level & REQ_IO_LOW) ||
+			(msm_host->caps_0 & CORE_1_8V_SUPPORT))
+		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
+					CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
+				CORE_VENDOR_SPEC);
+	/* Ensure that the IO PAD switches are updated before proceeding */
+	mb();
+
 	if (pwr_state)
 		msm_host->curr_pwr_state = pwr_state;
 	if (io_level)
@@ -1518,6 +1549,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 	}
 
 	/*
+	 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH bit can
+	 * be used as required later on.
+	 */
+	writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
+				CORE_IO_PAD_PWR_SWITCH_EN), host->ioaddr +
+			CORE_VENDOR_SPEC);
+	/*
 	 * Power on reset state may trigger power irq if previous status of
 	 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
 	 * interrupt in GIC, any pending power irq interrupt should be
-- 
 Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH RFC 2/2] mmc: sdhci-msm: support voltage pad switching

[Adrian Hunter]

On 18/01/18 10:05, Vijay Viswanath wrote:
> From: Krishna Konda <kkonda@codeaurora.org>
> 
> The PADs for sdhc controller are dual-voltage that support 3v/1.8v.
> Those PADs have a control signal (io_pad_pwr_switch/mode18 ) that
> indicates whether the PAD works in 3v or 1.8v.
> 
> SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
> based on actual voltage used for IO lines. So when power irq is
> triggered for io high or io low, the driver should check the voltages
> supported and set the pad accordingly.
> 
> Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
> ---

Not sure why this is RFC, but for sdhci:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

>  drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 5c23e92..f5728a8 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -78,6 +78,8 @@
>  #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
>  #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
>  #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
> +#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
> +#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
>  #define CORE_HC_SELECT_IN_EN	BIT(18)
>  #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>  #define CORE_HC_SELECT_IN_MASK	(7 << 19)
> @@ -1166,6 +1168,35 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
>  	 */
>  	writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
>  
> +	/*
> +	 * SDHC has core_mem and hc_mem device memory and these memory
> +	 * addresses do not fall within 1KB region. Hence, any update to
> +	 * core_mem address space would require an mb() to ensure this gets
> +	 * completed before its next update to registers within hc_mem.
> +	 */
> +	mb();
> +	/*
> +	 * We should unset IO PAD PWR switch only if the register write can
> +	 * set IO lines high and the regulator also switches to 3 V.
> +	 * Else, we should keep the IO PAD PWR switch set.
> +	 * This is applicable to certain targets where eMMC vccq supply is only
> +	 * 1.8V. In such targets, even during REQ_IO_HIGH, the IO PAD PWR
> +	 * switch must be kept set to reflect actual regulator voltage. This
> +	 * way, during initialization of controllers with only 1.8V, we will
> +	 * set the IO PAD bit without waiting for a REQ_IO_LOW.
> +	 */
> +	if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT))
> +		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
> +					~CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
> +				CORE_VENDOR_SPEC);
> +	else if ((io_level & REQ_IO_LOW) ||
> +			(msm_host->caps_0 & CORE_1_8V_SUPPORT))
> +		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
> +					CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
> +				CORE_VENDOR_SPEC);
> +	/* Ensure that the IO PAD switches are updated before proceeding */
> +	mb();
> +
>  	if (pwr_state)
>  		msm_host->curr_pwr_state = pwr_state;
>  	if (io_level)
> @@ -1518,6 +1549,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>  	}
>  
>  	/*
> +	 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH bit can
> +	 * be used as required later on.
> +	 */
> +	writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
> +				CORE_IO_PAD_PWR_SWITCH_EN), host->ioaddr +
> +			CORE_VENDOR_SPEC);
> +	/*
>  	 * Power on reset state may trigger power irq if previous status of
>  	 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
>  	 * interrupt in GIC, any pending power irq interrupt should be
> 

Re: [PATCH RFC 2/2] mmc: sdhci-msm: support voltage pad switching

[Bjorn Andersson]

On Thu 18 Jan 00:05 PST 2018, Vijay Viswanath wrote:

> From: Krishna Konda <kkonda@codeaurora.org>
> 
> The PADs for sdhc controller are dual-voltage that support 3v/1.8v.
> Those PADs have a control signal (io_pad_pwr_switch/mode18 ) that
> indicates whether the PAD works in 3v or 1.8v.
> 
> SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
> based on actual voltage used for IO lines. So when power irq is
> triggered for io high or io low, the driver should check the voltages
> supported and set the pad accordingly.
> 

I'll try to find some time to check that this doesn't break 8916 and
8974...again...

> Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
> ---
>  drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 5c23e92..f5728a8 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -78,6 +78,8 @@
>  #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
>  #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
>  #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
> +#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
> +#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
>  #define CORE_HC_SELECT_IN_EN	BIT(18)
>  #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>  #define CORE_HC_SELECT_IN_MASK	(7 << 19)
> @@ -1166,6 +1168,35 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
>  	 */
>  	writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
>  
> +	/*
> +	 * SDHC has core_mem and hc_mem device memory and these memory
> +	 * addresses do not fall within 1KB region. Hence, any update to
> +	 * core_mem address space would require an mb() to ensure this gets
> +	 * completed before its next update to registers within hc_mem.
> +	 */
> +	mb();

If you just use writel() instead of writel_relaxed() you don't need to
sprinkle the driver with comments like this. And you really should be
able to just say "Ensure ordering between core_mem and hc_mem writes" if
you really feel like making it explicit.

> +	/*
> +	 * We should unset IO PAD PWR switch only if the register write can
> +	 * set IO lines high and the regulator also switches to 3 V.
> +	 * Else, we should keep the IO PAD PWR switch set.
> +	 * This is applicable to certain targets where eMMC vccq supply is only
> +	 * 1.8V. In such targets, even during REQ_IO_HIGH, the IO PAD PWR
> +	 * switch must be kept set to reflect actual regulator voltage. This
> +	 * way, during initialization of controllers with only 1.8V, we will
> +	 * set the IO PAD bit without waiting for a REQ_IO_LOW.
> +	 */
> +	if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT))
> +		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
> +					~CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
> +				CORE_VENDOR_SPEC);

Please split this up in read, modify and write operations.

> +	else if ((io_level & REQ_IO_LOW) ||
> +			(msm_host->caps_0 & CORE_1_8V_SUPPORT))
> +		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
> +					CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
> +				CORE_VENDOR_SPEC);
> +	/* Ensure that the IO PAD switches are updated before proceeding */

That's not what "mb()" does, it ensures that any writes that was done
before this line will hit the hardware before any writes that is done
after this line.

But again, using writel() would save us from doing this explicitly
throughout the code.

> +	mb();
> +
>  	if (pwr_state)
>  		msm_host->curr_pwr_state = pwr_state;
>  	if (io_level)
> @@ -1518,6 +1549,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>  	}
>  
>  	/*
> +	 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH bit can
> +	 * be used as required later on.
> +	 */
> +	writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
> +				CORE_IO_PAD_PWR_SWITCH_EN), host->ioaddr +
> +			CORE_VENDOR_SPEC);

Please rewrite as 3 operations.

Do we need to set the pwr switch value as well? Or we're fine relying on
the existing value here?

Regards,
Bjorn

Re: [PATCH RFC 2/2] mmc: sdhci-msm: support voltage pad switching

[Vijay Viswanath]

On 2/3/2018 3:21 AM, Bjorn Andersson wrote:
> On Thu 18 Jan 00:05 PST 2018, Vijay Viswanath wrote:
> 
>> From: Krishna Konda <kkonda@codeaurora.org>
>>
>> The PADs for sdhc controller are dual-voltage that support 3v/1.8v.
>> Those PADs have a control signal (io_pad_pwr_switch/mode18 ) that
>> indicates whether the PAD works in 3v or 1.8v.
>>
>> SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
>> based on actual voltage used for IO lines. So when power irq is
>> triggered for io high or io low, the driver should check the voltages
>> supported and set the pad accordingly.
>>
> 
> I'll try to find some time to check that this doesn't break 8916 and
> 8974...again...
>

Thanks! Btwn, I had tested the code in db410c.

>> Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
>> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
>> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
>> ---
>>   drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 38 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>> index 5c23e92..f5728a8 100644
>> --- a/drivers/mmc/host/sdhci-msm.c
>> +++ b/drivers/mmc/host/sdhci-msm.c
>> @@ -78,6 +78,8 @@
>>   #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
>>   #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
>>   #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
>> +#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
>> +#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
>>   #define CORE_HC_SELECT_IN_EN	BIT(18)
>>   #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>>   #define CORE_HC_SELECT_IN_MASK	(7 << 19)
>> @@ -1166,6 +1168,35 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
>>   	 */
>>   	writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
>>   
>> +	/*
>> +	 * SDHC has core_mem and hc_mem device memory and these memory
>> +	 * addresses do not fall within 1KB region. Hence, any update to
>> +	 * core_mem address space would require an mb() to ensure this gets
>> +	 * completed before its next update to registers within hc_mem.
>> +	 */
>> +	mb();
> 
> If you just use writel() instead of writel_relaxed() you don't need to
> sprinkle the driver with comments like this. And you really should be
> able to just say "Ensure ordering between core_mem and hc_mem writes" if
> you really feel like making it explicit.
> 
>> +	/*
>> +	 * We should unset IO PAD PWR switch only if the register write can
>> +	 * set IO lines high and the regulator also switches to 3 V.
>> +	 * Else, we should keep the IO PAD PWR switch set.
>> +	 * This is applicable to certain targets where eMMC vccq supply is only
>> +	 * 1.8V. In such targets, even during REQ_IO_HIGH, the IO PAD PWR
>> +	 * switch must be kept set to reflect actual regulator voltage. This
>> +	 * way, during initialization of controllers with only 1.8V, we will
>> +	 * set the IO PAD bit without waiting for a REQ_IO_LOW.
>> +	 */
>> +	if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT))
>> +		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
>> +					~CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
>> +				CORE_VENDOR_SPEC);
> 
> Please split this up in read, modify and write operations.
> 

Will do

>> +	else if ((io_level & REQ_IO_LOW) ||
>> +			(msm_host->caps_0 & CORE_1_8V_SUPPORT))
>> +		writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
>> +					CORE_IO_PAD_PWR_SWITCH), host->ioaddr +
>> +				CORE_VENDOR_SPEC);
>> +	/* Ensure that the IO PAD switches are updated before proceeding */
> 
> That's not what "mb()" does, it ensures that any writes that was done
> before this line will hit the hardware before any writes that is done
> after this line.
> 

Will update the comments.

> But again, using writel() would save us from doing this explicitly
> throughout the code.
> 
>> +	mb();
>> +
>>   	if (pwr_state)
>>   		msm_host->curr_pwr_state = pwr_state;
>>   	if (io_level)
>> @@ -1518,6 +1549,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>   	}
>>   
>>   	/*
>> +	 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH bit can
>> +	 * be used as required later on.
>> +	 */
>> +	writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
>> +				CORE_IO_PAD_PWR_SWITCH_EN), host->ioaddr +
>> +			CORE_VENDOR_SPEC);
> 
> Please rewrite as 3 operations.
> 
> Do we need to set the pwr switch value as well? Or we're fine relying on
> the existing value here?

After the IO_PAD_PWR_SWTCH is enabled, we will call 
sdhci_msm_handle_pwr_irq. If there is any pending power irq interrupt, 
that will set the appropriate pwr switch value. Otherwise, an 
appropriate value will get set during REQ_BUS_ON event.

> 
> Regards,
> Bjorn
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