From: Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH 2/6] drm/msm: Add new PM4 type7 opcodes
Date: Thu, 8 Mar 2018 11:36:21 +0530 [thread overview]
Message-ID: <1520489185-21828-3-git-send-email-smasetty@codeaurora.org> (raw)
In-Reply-To: <1520489185-21828-1-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
This patch adds the following two opcodes:
CP_SET_MARKER opcode is a way to tell CP the current mode of GPU
operation(useful if preemption is in use).
CP_SET_PSEUDO_REG opcode will instruct CP to set a bunch of internal
CP registers, again useful for the preemption save/restore sequence.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index fb605a3..f0fd80e 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -202,6 +202,8 @@ enum adreno_pm4_type3_packets {
CP_EXEC_CS = 51,
CP_PERFCOUNTER_ACTION = 80,
CP_SMMU_TABLE_UPDATE = 83,
+ CP_SET_MARKER = 101,
+ CP_SET_PSEUDO_REG = 86,
CP_CONTEXT_REG_BUNCH = 92,
CP_YIELD_ENABLE = 28,
CP_SKIP_IB2_ENABLE_GLOBAL = 29,
--
1.9.1
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next prev parent reply other threads:[~2018-03-08 6:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-08 6:06 [PATCH 0/6] Preemption support for A6xx targets Sharat Masetty
2018-03-08 6:06 ` [PATCH 1/6] drm/msm: Add submitqueue setup and close Sharat Masetty
[not found] ` <1520489185-21828-1-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-03-08 6:06 ` Sharat Masetty [this message]
2018-03-08 6:06 ` [PATCH 5/6] drm/msm/Adreno: Refactor some preemption code Sharat Masetty
2018-03-08 6:06 ` [PATCH 3/6] drm/msm/A6xx: Implement preemption for A6XX targets Sharat Masetty
2018-03-08 6:06 ` [PATCH 4/6] drm/msm/A6xx: Enable preemption for A6xx targets Sharat Masetty
2018-03-08 6:06 ` [PATCH 6/6] drm/msm/A6xx: Enable L1 preemption level Sharat Masetty
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