From: Amit Nischal <anischal@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
Odelu Kukatla <okukatla@codeaurora.org>,
Taniya Das <tdas@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Amit Nischal <anischal@codeaurora.org>
Subject: [PATCH v2 0/4] Misc patches to support clocks for SDM845
Date: Thu, 8 Mar 2018 12:48:11 +0530 [thread overview]
Message-ID: <1520493495-3084-1-git-send-email-anischal@codeaurora.org> (raw)
Changes in v2:
Fixup for recalc_rate ops for clk_rcg2_shared_ops:
There could be few scenarios where shared clocks are configured
at rate other than CXO by boot. In those cases there would be a
mismatch between the rate calculated by the recalc shared ops
and the actual HW register configuration. Fix the same by adding
an additional check to read current src from CFG register and
make a decision based on that.
Changes in v1:
https://lkml.org/lkml/2018/1/31/209
This patch series does the miscellaneous changes to support
clock nodes for SDM845. Below are the major changes for
which the existing code does not have support.
1. Clear hardware clock control bit of RCGs where HW clock
control bit is set by default so that software can control
those root clocks.
2. Introduces clk_rcg2_shared_ops to support clock controller
drivers for SDM845. With new shared ops, RCGs with shared
branches will be configured to a safe source in disable
path and actual RCG update configuration will be done in
enable path instead of doing config update in set_rate.
In set_rate(), just cache the rate instead of doing actual
configuration update. Also each RCG in clock controller
driver will have their own safe configuration frequency
table to switch to safe frequency.
3. Add support for controlling Fabia PLL for which the support
is not available in existing alpha PLL code.
4. Add Global Clock controller (GCC) driver for SDM845. This
should allow most non-multimedia device drivers to probe
and control their clocks.
Amit Nischal (3):
clk: qcom: Clear hardware clock control bit of RCG
clk: qcom: Configure the RCGs to a safe source as needed
clk: qcom: Add support for controlling Fabia PLL
Taniya Das (1):
clk: qcom: Add Global Clock controller (GCC) driver for SDM845
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 324 +-
drivers/clk/qcom/clk-alpha-pll.h | 18 +-
drivers/clk/qcom/clk-rcg.h | 8 +-
drivers/clk/qcom/clk-rcg2.c | 160 +-
drivers/clk/qcom/gcc-sdm845.c | 3619 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdm845.h | 242 ++
9 files changed, 4373 insertions(+), 11 deletions(-)
create mode 100644 drivers/clk/qcom/gcc-sdm845.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next reply other threads:[~2018-03-08 7:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-08 7:18 Amit Nischal [this message]
2018-03-08 7:18 ` [PATCH v2 1/4] clk: qcom: Clear hardware clock control bit of RCG Amit Nischal
2018-03-19 22:55 ` Stephen Boyd
2018-03-26 5:19 ` Nischal, Amit
2018-03-08 7:18 ` [PATCH v2 2/4] clk: qcom: Configure the RCGs to a safe source as needed Amit Nischal
2018-03-20 0:30 ` Stephen Boyd
2018-04-03 8:52 ` Amit Nischal
2018-03-08 7:18 ` [PATCH v2 3/4] clk: qcom: Add support for controlling Fabia PLL Amit Nischal
2018-03-19 23:33 ` Stephen Boyd
2018-03-08 7:18 ` [PATCH v2 4/4] clk: qcom: Add Global Clock controller (GCC) driver for SDM845 Amit Nischal
2018-03-20 0:42 ` Stephen Boyd
2018-04-03 12:24 ` Amit Nischal
2018-04-05 22:57 ` Stephen Boyd
2018-04-09 5:25 ` Amit Nischal
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