From: Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH 2/5] arm64:dts:sdm845: Add support for GPU LLCC
Date: Fri, 23 Mar 2018 12:49:48 +0530 [thread overview]
Message-ID: <1521789591-28628-3-git-send-email-smasetty@codeaurora.org> (raw)
In-Reply-To: <1521789591-28628-1-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Add client side bindings required for the GPU to use the last level
system cache. Also add a register range in the GPU CX domain.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index eb0a1b2..7e2d938 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -887,8 +887,8 @@
compatible = "qcom,adreno-630.2", "qcom,adreno";
#stream-id-cells = <16>;
- reg = <0x5000000 0x40000>;
- reg-names = "kgsl_3d0_reg_memory";
+ reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem";
/*
* Look ma, no clocks! The GPU clocks and power are controlled
@@ -898,6 +898,10 @@
interrupts = <0 300 0>;
interrupt-names = "kgsl_3d0_irq";
+ /* GPU related llc slices */
+ cache-slice-names = "gpu", "gpuhtw";
+ cache-slices = <&llcc 12>, <&llcc 11>;
+
iommus = <&kgsl_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
--
1.9.1
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next prev parent reply other threads:[~2018-03-23 7:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-23 7:19 [PATCH 0/5] Adreno A6xx system cache support Sharat Masetty
2018-03-23 7:19 ` [PATCH 4/5] drm/msm: Pass mmu features to generic layers Sharat Masetty
2018-04-03 21:22 ` [Freedreno] " Jordan Crouse
[not found] ` <1521789591-28628-5-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-05 6:47 ` Vivek Gautam
[not found] ` <1521789591-28628-1-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-03-23 7:19 ` [PATCH 1/5] drm/msm: rearrange the gpu_rmw() function Sharat Masetty
[not found] ` <1521789591-28628-2-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-03 21:20 ` Jordan Crouse
2018-03-23 7:19 ` Sharat Masetty [this message]
[not found] ` <1521789591-28628-3-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-03 21:22 ` [PATCH 2/5] arm64:dts:sdm845: Add support for GPU LLCC Jordan Crouse
[not found] ` <20180403212211.GF22210-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org>
2018-04-05 5:20 ` Sharat Masetty
2018-04-05 6:52 ` Vivek Gautam
2018-03-23 7:19 ` [PATCH 3/5] drm/msm/adreno: Add registers in the GPU CX domain Sharat Masetty
2018-04-03 21:22 ` [Freedreno] " Jordan Crouse
2018-03-23 7:19 ` [PATCH 5/5] drm/msm/A6xx: Add support for using system cache(llc) Sharat Masetty
[not found] ` <1521789591-28628-6-git-send-email-smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-03 21:24 ` Jordan Crouse
2018-04-05 5:25 ` [Freedreno] " Sharat Masetty
2018-04-05 7:04 ` Vivek Gautam
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