From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sinan Kaya Subject: [PATCH v6 5/7] fm10k: Eliminate duplicate barriers on weakly-ordered archs Date: Fri, 23 Mar 2018 14:21:15 -0400 Message-ID: <1521829277-9398-6-git-send-email-okaya@codeaurora.org> References: <1521829277-9398-1-git-send-email-okaya@codeaurora.org> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1521829277-9398-1-git-send-email-okaya@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: jeffrey.t.kirsher@intel.com Cc: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/fm10k/fm10k_main.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_main.c b/drivers/net/ethernet/intel/fm10k/fm10k_main.c index 409554d..360ff9b 100644 --- a/drivers/net/ethernet/intel/fm10k/fm10k_main.c +++ b/drivers/net/ethernet/intel/fm10k/fm10k_main.c @@ -180,7 +180,12 @@ void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count) wmb(); /* notify hardware of new descriptors */ - writel(i, rx_ring->tail); + writel_relaxed(i, rx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); } } @@ -1055,7 +1060,7 @@ static void fm10k_tx_map(struct fm10k_ring *tx_ring, /* notify HW of packet */ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems -- 2.7.4