From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jeff Kirsher Subject: Re: [PATCH v7 0/7] netdev: intel: Eliminate duplicate barriers on weakly-ordered archs Date: Fri, 23 Mar 2018 16:58:16 -0700 Message-ID: <1521849496.15055.16.camel@intel.com> References: <1521831180-25014-1-git-send-email-okaya@codeaurora.org> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2974045116122358540==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Alexander Duyck , Sinan Kaya , intel-wired-lan Cc: Netdev , Timur Tabi , sulrich@codeaurora.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org --===============2974045116122358540== Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-L47iPZOtkSJJQNM/yD2b" --=-L47iPZOtkSJJQNM/yD2b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2018-03-23 at 14:53 -0700, Alexander Duyck wrote: > On Fri, Mar 23, 2018 at 11:52 AM, Sinan Kaya > wrote: > > Code includes wmb() followed by writel() in multiple places. writel() > > already has a barrier on some architectures like arm64. > >=20 > > This ends up CPU observing two barriers back to back before executing > > the > > register write. > >=20 > > Since code already has an explicit barrier call, changing writel() to > > writel_relaxed(). > >=20 > > I did a regex search for wmb() followed by writel() in each drivers > > directory. > > I scrubbed the ones I care about in this series. > >=20 > > I considered "ease of change", "popular usage" and "performance > > critical > > path" as the determining criteria for my filtering. > >=20 > > We used relaxed API heavily on ARM for a long time but > > it did not exist on other architectures. For this reason, relaxed > > architectures have been paying double penalty in order to use the > > common > > drivers. > >=20 > > Now that relaxed API is present on all architectures, we can go and > > scrub > > all drivers to see what needs to change and what can remain. > >=20 > > We start with mostly used ones and hope to increase the coverage over > > time. > > It will take a while to cover all drivers. > >=20 > > Feel free to apply patches individually. >=20 > I looked over the set and they seem good. >=20 > Reviewed-by: Alexander Duyck Grrr, patch 1 does not apply cleanly to my next-queue tree (dev-queue branch). I will deal with this series in a day or two, after I have dealt with my driver pull requests. > >=20 > > Changes since v6: > > clean up between 2..6 and then make your Alex's changes on 1 and 7 > > The mmiowb shouldn't be needed for Rx. Only one CPU will be running > > NAPI for the queue and we will synchronize this with a full writel > > anyway when we re-enable the interrupts. > >=20 > > Sinan Kaya (7): > > i40e/i40evf: Eliminate duplicate barriers on weakly-ordered archs > > ixgbe: eliminate duplicate barriers on weakly-ordered archs > > igbvf: eliminate duplicate barriers on weakly-ordered archs > > igb: eliminate duplicate barriers on weakly-ordered archs > > fm10k: Eliminate duplicate barriers on weakly-ordered archs > > ixgbevf: keep writel() closer to wmb() > > ixgbevf: eliminate duplicate barriers on weakly-ordered archs > >=20 > > drivers/net/ethernet/intel/fm10k/fm10k_main.c | 4 ++-- > > drivers/net/ethernet/intel/i40e/i40e_txrx.c | 14 ++++++++++---- > > drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 4 ++-- > > drivers/net/ethernet/intel/igb/igb_main.c | 4 ++-- > > drivers/net/ethernet/intel/igbvf/netdev.c | 4 ++-- > > drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 8 ++++---- > > drivers/net/ethernet/intel/ixgbevf/ixgbevf.h | 5 ----- > > drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c | 11 ++++++++--- > > 8 files changed, 30 insertions(+), 24 deletions(-) > >=20 > > -- > > 2.7.4 > >=20 --=-L47iPZOtkSJJQNM/yD2b Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiTyZWz+nnTrOJ1LZ5W/vlVpL7c4FAlq1lJgACgkQ5W/vlVpL 7c6bxQ/9GIz6z3XaBAf1B+xgisYSwSpzFj3/x/EVDmY0PROUqA0NbHbLxbXtsThY BZ6d9KkAuO7UX21CZgrOk62ysWaJY3bX2dMKzQmxWAiX0At2DeV4IBx6bfxzqf6o EdvsLfO4AA15U6QoAT+nXk3tx948gvGf8YaMZw54qgHnqTKcznC1Ms6alqnZ4G0J /c9WNvRHnzDs9uLbw4YW3l90i/QGnsNUZHL9A/+Tv6o5mHDzRar1XYxee84USMTg M3eZmce3xm2gE+rCU+p3HaTD9N2LVUY0STAcKen2FrcNI9TI8E0MxqYzp9XigT2D oz2ByiaXOtF/bynf9MTFPhVfl7m6RpB3ZX42N4rRledqwq69LIZ48Wz3RMKiHFzA j+3gLoJ/PsSp2LvaPl8aycLm9cM6asfQ4HA4muY72sMrn+WtrwaISj8c+PAuMqYl boQ88Zb6Y87JJSjeq06cg/T2R5XaBFO/p151ah4ZL9dCODnYKqWu9h7LuPJntFQw q7LZS19KkoLDPSpLOTOVKe4AXg7+Pbk/OQ/Ug5VFb5QcYQN7pys1sQnfAxegBzv/ cSYgO3NfhSfTX9HKH+k4QE3Jvb5/EoUv1dlvDH93W6v1t3glymPGNpQOVt/VocOn QlswR3XJ3Irru/GwKS3+Y4RVl6DeMtv4ziubzikxiZKGaup2pLA= =tiGK -----END PGP SIGNATURE----- --=-L47iPZOtkSJJQNM/yD2b-- --===============2974045116122358540== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============2974045116122358540==--