* [PATCH v2 0/3] Update reset and poll logic for GDSCs
@ 2018-04-09 8:37 Taniya Das
0 siblings, 0 replies; 2+ messages in thread
From: Taniya Das @ 2018-04-09 8:37 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Andy Gross, David Brown, Rajendra Nayak, Odelu Kukatla,
Amit Nischal, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
Taniya Das
[v2]
* Addressed review comments given in v1 series
This series implements the below logic for the GDSCs
1. logic to reset the AON logic before or assert/deassert the block
control reset removing the clamp io for few GDSCs on SDM845 SoC.
2. It also introduces the requirement to poll for higher timeout values
for few of the GDSCs.
3. There is a new poll register for the GDSCs on SDM845 SoCs which needs
to be polled for the correct hardware status of the GDSCs.
Amit Nischal (3):
clk: qcom: gdsc: Add support to reset AON and block reset logic
clk: qcom: gdsc: Add support to poll for higher timeout value
clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
drivers/clk/qcom/gdsc.c | 63 +++++++++++++++++++++++++++++++++++++++++++------
drivers/clk/qcom/gdsc.h | 5 +++-
2 files changed, 60 insertions(+), 8 deletions(-)
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH v2 0/3] Update reset and poll logic for GDSCs
@ 2018-04-09 8:41 Taniya Das
0 siblings, 0 replies; 2+ messages in thread
From: Taniya Das @ 2018-04-09 8:41 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Andy Gross, David Brown, Rajendra Nayak, Odelu Kukatla,
Amit Nischal, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
Taniya Das
[v2]
* Addressed review comments given in v1 series
This series implements the below logic for the GDSCs
1. logic to reset the AON logic before or assert/deassert the block
control reset removing the clamp io for few GDSCs on SDM845 SoC.
2. It also introduces the requirement to poll for higher timeout values
for few of the GDSCs.
3. There is a new poll register for the GDSCs on SDM845 SoCs which needs
to be polled for the correct hardware status of the GDSCs.
Amit Nischal (3):
clk: qcom: gdsc: Add support to reset AON and block reset logic
clk: qcom: gdsc: Add support to poll for higher timeout value
clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
drivers/clk/qcom/gdsc.c | 63 +++++++++++++++++++++++++++++++++++++++++++------
drivers/clk/qcom/gdsc.h | 5 +++-
2 files changed, 60 insertions(+), 8 deletions(-)
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply [flat|nested] 2+ messages in thread
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