From: Sinan Kaya <okaya@codeaurora.org>
To: linux-mips@linux-mips.org, arnd@arndb.de, timur@codeaurora.org,
sulrich@codeaurora.org
Cc: linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Sinan Kaya <okaya@codeaurora.org>,
Ralf Baechle <ralf@linux-mips.org>,
James Hogan <jhogan@kernel.org>,
Paul Burton <paul.burton@mips.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
Date: Thu, 12 Apr 2018 22:30:44 -0400 [thread overview]
Message-ID: <1523586646-19630-2-git-send-email-okaya@codeaurora.org> (raw)
In-Reply-To: <1523586646-19630-1-git-send-email-okaya@codeaurora.org>
While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index fd00ddaf..d96af41 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA dma prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
--
2.7.4
next prev parent reply other threads:[~2018-04-13 2:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-13 2:30 [PATCH v4 1/2] MIPS: io: prevent compiler reordering on the default writeX() implementation Sinan Kaya
2018-04-13 2:30 ` Sinan Kaya [this message]
2018-04-13 2:33 ` [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX() Sinan Kaya
2018-04-13 23:52 ` James Hogan
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