From: Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH] rnndb: Add additional a6xx registers in gpu CX
Date: Mon, 8 Oct 2018 19:10:30 +0530 [thread overview]
Message-ID: <1539006030-10442-1-git-send-email-smasetty@codeaurora.org> (raw)
Add a few additional registers in the CX domain needed to implement
system cache support for a6xx.
---
rnndb/adreno/a6xx.xml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
index b2bd64b..78ba1ce 100644
--- a/rnndb/adreno/a6xx.xml
+++ b/rnndb/adreno/a6xx.xml
@@ -2963,4 +2963,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
</domain>
+<domain name="A6XX_CX_MISC" width="32">
+ <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
+ <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
+</domain>
+
</database>
--
1.9.1
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reply other threads:[~2018-10-08 13:40 UTC|newest]
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