[PATCH 0/6] arm64: dts: DB820c: Add display and audio support

[PATCH 0/6] arm64: dts: DB820c: Add display and audio support

[Srinivas Kandagatla]

Hi Andy, 

Now that most of the bits are in mainline, its good time to add display
and audio support to DB820c.
These patches are being tested in integration branch from long time.

Am resending 2 SMMU patches (https://patchwork.kernel.org/cover/10726329/)
in this series to keep all the display and sound patches together.

Can you pick these up for 5.1

thanks,
srini

Archit Taneja (3):
  arm64: dts: msm8996: Add display smmu node
  arm64: qcom: msm8996.dtsi: Add Display nodes
  arm64: dts: apq8096-db820c: Add HDMI display support

Jordan Crouse (2):
  arm64: dts: msm8996: Add graphics smmu node
  arm64: dts: Add Adreno GPU and GPU smmu definitions

Srinivas Kandagatla (1):
  arm64: dts: db820c: Add sound card support

 .../boot/dts/qcom/apq8096-db820c-pins.dtsi    |  52 +++
 .../dts/qcom/apq8096-db820c-pmic-pins.dtsi    |   9 +
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi  | 125 +++++++
 arch/arm64/boot/dts/qcom/msm8996-pins.dtsi    |  46 +++
 arch/arm64/boot/dts/qcom/msm8996.dtsi         | 346 ++++++++++++++++++
 5 files changed, 578 insertions(+)

-- 
2.20.1

[PATCH 1/6] arm64: dts: msm8996: Add graphics smmu node

[Srinivas Kandagatla]

From: Jordan Crouse <jcrouse@codeaurora.org>

Add device node for graphics smmu, aka. adreno_smmu.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 6ba96916c66d..c9b80d175fd4 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1138,6 +1138,23 @@
 			};
 		};
 
+		adreno_smmu: arm,smmu@b40000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0xb40000 0x10000>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+
+			clocks = <&mmcc GPU_AHB_CLK>,
+				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+			clock-names = "iface", "bus";
+
+			power-domains = <&mmcc GPU_GDSC>;
+		};
+
 		agnoc@0 {
 			power-domains = <&gcc AGGRE0_NOC_GDSC>;
 			compatible = "simple-pm-bus";
-- 
2.20.1

[PATCH 2/6] arm64: dts: msm8996: Add display smmu node

[Srinivas Kandagatla]

From: Archit Taneja <architt@codeaurora.org>

Add device node for display smmu, aka. mdp_smmu.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c9b80d175fd4..96adda520bd5 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1155,6 +1155,23 @@
 			power-domains = <&mmcc GPU_GDSC>;
 		};
 
+		mdp_smmu: arm,smmu@d00000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0xd00000 0x10000>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+
+			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
+				 <&mmcc SMMU_MDP_AXI_CLK>;
+			clock-names = "iface", "bus";
+
+			power-domains = <&mmcc MDSS_GDSC>;
+		};
+
 		agnoc@0 {
 			power-domains = <&gcc AGGRE0_NOC_GDSC>;
 			compatible = "simple-pm-bus";
-- 
2.20.1

[PATCH 3/6] arm64: qcom: msm8996.dtsi: Add Display nodes

[Srinivas Kandagatla]

From: Archit Taneja <architt@codeaurora.org>

Signed-off-by: Archit Taneja <architt@codeaurora.org>
[Removed instances of mmagic clocks;
Use qcom,msm8996-smmu-v2 bindings]
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 120 ++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 96adda520bd5..0d0b9482aa4d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1337,6 +1337,126 @@
 						"bus_slave";
 			};
 		};
+
+		mdss: mdss@900000 {
+			compatible = "qcom,mdss";
+
+			reg = <0x900000 0x1000>,
+			      <0x9b0000 0x1040>,
+			      <0x9b8000 0x1040>;
+			reg-names = "mdss_phys",
+				    "vbif_phys",
+				    "vbif_nrt_phys";
+
+			power-domains = <&mmcc MDSS_GDSC>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			clocks = <&mmcc MDSS_AHB_CLK>;
+			clock-names = "iface_clk";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdp: mdp@901000 {
+				compatible = "qcom,mdp5";
+				reg = <0x901000 0x90000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc SMMU_MDP_AXI_CLK>,
+					 <&mmcc MDSS_VSYNC_CLK>;
+				clock-names = "iface_clk",
+					      "bus_clk",
+					      "core_clk",
+					      "iommu_clk",
+					      "vsync_clk";
+
+				iommus = <&mdp_smmu 0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdp5_intf3_out: endpoint {
+							remote-endpoint = <&hdmi_in>;
+						};
+					};
+				};
+			};
+
+			hdmi: hdmi-tx@9a0000 {
+				compatible = "qcom,hdmi-tx-8996";
+				reg =	<0x009a0000 0x50c>,
+					<0x00070000 0x6158>,
+					<0x009e0000 0xfff>;
+				reg-names = "core_physical",
+					    "qfprom_physical",
+					    "hdcp_physical";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_HDMI_CLK>,
+					 <&mmcc MDSS_HDMI_AHB_CLK>,
+					 <&mmcc MDSS_EXTPCLK_CLK>;
+				clock-names =
+					"mdp_core_clk",
+					"iface_clk",
+					"core_clk",
+					"alt_iface_clk",
+					"extp_clk";
+
+				phys = <&hdmi_phy>;
+				phy-names = "hdmi_phy";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						hdmi_in: endpoint {
+							remote-endpoint = <&mdp5_intf3_out>;
+						};
+					};
+				};
+			};
+
+			hdmi_phy: hdmi-phy@9a0600 {
+				#phy-cells = <0>;
+				compatible = "qcom,hdmi-phy-8996";
+				reg = <0x9a0600 0x1c4>,
+				      <0x9a0a00 0x124>,
+				      <0x9a0c00 0x124>,
+				      <0x9a0e00 0x124>,
+				      <0x9a1000 0x124>,
+				      <0x9a1200 0x0c8>;
+				reg-names = "hdmi_pll",
+					    "hdmi_tx_l0",
+					    "hdmi_tx_l1",
+					    "hdmi_tx_l2",
+					    "hdmi_tx_l3",
+					    "hdmi_phy";
+
+				clocks = <&mmcc MDSS_AHB_CLK>,
+					 <&gcc GCC_HDMI_CLKREF_CLK>;
+				clock-names = "iface_clk",
+					      "ref_clk";
+			};
+		};
 	};
 
 	adsp-pil {
-- 
2.20.1

[PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Srinivas Kandagatla]

From: Jordan Crouse <jcrouse@codeaurora.org>

Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
[Remove mmagic clocks from GPU/smmu nodes]
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0d0b9482aa4d..b5f23594905c 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -84,6 +84,12 @@
 			qcom,client-id = <1>;
 			qcom,vmid = <15>;
 		};
+
+		zap_shader_region: gpu@8f200000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x90b00000 0x0 0xa00000>;
+			no-map;
+		};
 	};
 
 	cpus {
@@ -1338,6 +1344,52 @@
 			};
 		};
 
+		gpu@b00000 {
+			compatible = "qcom,adreno-530.2", "qcom,adreno";
+			#stream-id-cells = <16>;
+
+			reg = <0xb00000 0x3f000>;
+			reg-names = "kgsl_3d0_reg_memory";
+
+			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+
+			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+				<&mmcc GPU_AHB_CLK>,
+				<&mmcc GPU_GX_RBBMTIMER_CLK>,
+				<&gcc GCC_BIMC_GFX_CLK>,
+				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+			clock-names = "core",
+				"iface",
+				"rbbmtimer",
+				"mem",
+				"mem_iface";
+
+			power-domains = <&mmcc GPU_GDSC>;
+			iommus = <&adreno_smmu 0>;
+
+			qcom,gpu-quirk-two-pass-use-wfi;
+			qcom,gpu-quirk-fault-detect-mask;
+
+			/* This is a safe speed for bring up in all bin levels.
+			 * This isn't the fastest the chip can go, but we can
+			 * get there eventually */
+			qcom,gpu-pwrlevels {
+				compatible = "qcom,gpu-pwrlevels";
+				qcom,gpu-pwrlevel@0 {
+					qcom,gpu-freq = <510000000>;
+				};
+				qcom,gpu-pwrlevel@1 {
+					qcom,gpu-freq = <27000000>;
+				};
+			};
+
+			zap-shader {
+				memory-region = <&zap_shader_region>;
+			};
+		};
+
 		mdss: mdss@900000 {
 			compatible = "qcom,mdss";
 
-- 
2.20.1

Re: [PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Jordan Crouse]

On Tue, Jan 29, 2019 at 01:23:33PM +0000, Srinivas Kandagatla wrote:
> From: Jordan Crouse <jcrouse@codeaurora.org>
> 
> Add an initial node for the Adreno GPU and it's companion
> SMMU. The GPU node is mostly complete except for a bare
> bones power table that will be filled out more completely
> later.
> 
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> [Remove mmagic clocks from GPU/smmu nodes]
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

Thanks for sending this.

> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 0d0b9482aa4d..b5f23594905c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -84,6 +84,12 @@
>  			qcom,client-id = <1>;
>  			qcom,vmid = <15>;
>  		};
> +
> +		zap_shader_region: gpu@8f200000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x90b00000 0x0 0xa00000>;
> +			no-map;
> +		};
>  	};
>  
>  	cpus {
> @@ -1338,6 +1344,52 @@
>  			};
>  		};
>  
> +		gpu@b00000 {
> +			compatible = "qcom,adreno-530.2", "qcom,adreno";
> +			#stream-id-cells = <16>;
> +
> +			reg = <0xb00000 0x3f000>;
> +			reg-names = "kgsl_3d0_reg_memory";
> +
> +			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "kgsl_3d0_irq";

We dropped the interrupt name as of:

https://cgit.freedesktop.org/~robclark/linux/commit/?h=msm-next&id=2255f244f92e651dbd410f92d2968c6dae4ead8e

You should be able to safely omit it.

> +
> +			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
> +				<&mmcc GPU_AHB_CLK>,
> +				<&mmcc GPU_GX_RBBMTIMER_CLK>,
> +				<&gcc GCC_BIMC_GFX_CLK>,
> +				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
> +
> +			clock-names = "core",
> +				"iface",
> +				"rbbmtimer",
> +				"mem",
> +				"mem_iface";
> +
> +			power-domains = <&mmcc GPU_GDSC>;
> +			iommus = <&adreno_smmu 0>;
> +
> +			qcom,gpu-quirk-two-pass-use-wfi;
> +			qcom,gpu-quirk-fault-detect-mask;

This was downstream silliness - neither of these "flags" made it upstream
(thankfully).

> +
> +			/* This is a safe speed for bring up in all bin levels.
> +			 * This isn't the fastest the chip can go, but we can
> +			 * get there eventually */
> +			qcom,gpu-pwrlevels {
> +				compatible = "qcom,gpu-pwrlevels";
> +				qcom,gpu-pwrlevel@0 {
> +					qcom,gpu-freq = <510000000>;
> +				};
> +				qcom,gpu-pwrlevel@1 {
> +					qcom,gpu-freq = <27000000>;
> +				};

Hmm - I haven't looked at the integration branch in a while but I'm positive
that we had opp tables at some point because the driver supports
opp-supported-hw. I hope I didn't just leave that sitting on my hard drive
somewhere. I'll check and let you know.

Jordan


> +			};
> +
> +			zap-shader {
> +				memory-region = <&zap_shader_region>;
> +			};
> +		};
> +
>  		mdss: mdss@900000 {
>  			compatible = "qcom,mdss";
>  
> -- 
> 2.20.1
> 

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Jordan Crouse]

On Tue, Jan 29, 2019 at 09:04:26AM -0700, Jordan Crouse wrote:
> On Tue, Jan 29, 2019 at 01:23:33PM +0000, Srinivas Kandagatla wrote:
> > From: Jordan Crouse <jcrouse@codeaurora.org>
> > 
> > Add an initial node for the Adreno GPU and it's companion
> > SMMU. The GPU node is mostly complete except for a bare
> > bones power table that will be filled out more completely
> > later.
> > 
> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> > [Remove mmagic clocks from GPU/smmu nodes]
> > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> 
> Thanks for sending this.
> 
> > ---
> >  arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++
> >  1 file changed, 52 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> > index 0d0b9482aa4d..b5f23594905c 100644
> > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> > @@ -84,6 +84,12 @@
> >  			qcom,client-id = <1>;
> >  			qcom,vmid = <15>;
> >  		};
> > +
> > +		zap_shader_region: gpu@8f200000 {
> > +			compatible = "shared-dma-pool";
> > +			reg = <0x0 0x90b00000 0x0 0xa00000>;
> > +			no-map;
> > +		};
> >  	};
> >  
> >  	cpus {
> > @@ -1338,6 +1344,52 @@
> >  			};
> >  		};
> >  
> > +		gpu@b00000 {
> > +			compatible = "qcom,adreno-530.2", "qcom,adreno";
> > +			#stream-id-cells = <16>;
> > +
> > +			reg = <0xb00000 0x3f000>;
> > +			reg-names = "kgsl_3d0_reg_memory";
> > +
> > +			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "kgsl_3d0_irq";
> 
> We dropped the interrupt name as of:
> 
> https://cgit.freedesktop.org/~robclark/linux/commit/?h=msm-next&id=2255f244f92e651dbd410f92d2968c6dae4ead8e
> 
> You should be able to safely omit it.
> 
> > +
> > +			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
> > +				<&mmcc GPU_AHB_CLK>,
> > +				<&mmcc GPU_GX_RBBMTIMER_CLK>,
> > +				<&gcc GCC_BIMC_GFX_CLK>,
> > +				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
> > +
> > +			clock-names = "core",
> > +				"iface",
> > +				"rbbmtimer",
> > +				"mem",
> > +				"mem_iface";
> > +
> > +			power-domains = <&mmcc GPU_GDSC>;
> > +			iommus = <&adreno_smmu 0>;
> > +
> > +			qcom,gpu-quirk-two-pass-use-wfi;
> > +			qcom,gpu-quirk-fault-detect-mask;
> 
> This was downstream silliness - neither of these "flags" made it upstream
> (thankfully).
> 
> > +
> > +			/* This is a safe speed for bring up in all bin levels.
> > +			 * This isn't the fastest the chip can go, but we can
> > +			 * get there eventually */
> > +			qcom,gpu-pwrlevels {
> > +				compatible = "qcom,gpu-pwrlevels";
> > +				qcom,gpu-pwrlevel@0 {
> > +					qcom,gpu-freq = <510000000>;
> > +				};
> > +				qcom,gpu-pwrlevel@1 {
> > +					qcom,gpu-freq = <27000000>;
> > +				};
> 
> Hmm - I haven't looked at the integration branch in a while but I'm positive
> that we had opp tables at some point because the driver supports
> opp-supported-hw. I hope I didn't just leave that sitting on my hard drive
> somewhere. I'll check and let you know.

Ugh, I just found them sitting unsent in a dusty git branch. I can either send
them as incremental patches on top of yours to be squashed later or I can
refactor this patch and send it out again, whatever is easiest for you.

Jordan

> > +			};
> > +
> > +			zap-shader {
> > +				memory-region = <&zap_shader_region>;
> > +			};
> > +		};
> > +
> >  		mdss: mdss@900000 {
> >  			compatible = "qcom,mdss";
> >  
> > -- 
> > 2.20.1
> > 
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Srinivas Kandagatla]

Thanks Jordan,

On 29/01/2019 16:43, Jordan Crouse wrote:
> Ugh, I just found them sitting unsent in a dusty git branch. I can either send
> them as incremental patches on top of yours to be squashed later or I can
> refactor this patch and send it out again, whatever is easiest for you.

If you can refactor this patch and send it out, that would be great!

thanks,
srini

[PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Jordan Crouse]

Add an initial node for the Adreno GPU and it's companion
SMMU.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
This is slightly updated version of [1] to include a correct OPP table and other
such stuff. I didn't know the best way to send it, so I attached it to the
original email and hopefully Andy forgives me. Otherwise, Srinivas can resend
it correctly.

[1] https://patchwork.kernel.org/patch/10786185/

 arch/arm64/boot/dts/qcom/msm8996.dtsi | 86 +++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0d0b948..0950415 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -84,6 +84,12 @@
 			qcom,client-id = <1>;
 			qcom,vmid = <15>;
 		};
+
+		zap_shader_region: gpu@8f200000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x90b00000 0x0 0xa00000>;
+			no-map;
+		};
 	};
 
 	cpus {
@@ -796,6 +802,11 @@
 				reg = <0x24f 0x1>;
 				bits = <1 4>;
 			};
+
+			gpu_speed_bin: gpu_speed_bin@133 {
+				reg = <0x133 0x1>;
+				bits = <5 3>;
+			};
 		};
 
 		phy@34000 {
@@ -1338,6 +1349,81 @@
 			};
 		};
 
+		gpu@b00000 {
+			compatible = "qcom,adreno-530.2", "qcom,adreno";
+			#stream-id-cells = <16>;
+
+			reg = <0xb00000 0x3f000>;
+			reg-names = "kgsl_3d0_reg_memory";
+
+			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+				<&mmcc GPU_AHB_CLK>,
+				<&mmcc GPU_GX_RBBMTIMER_CLK>,
+				<&gcc GCC_BIMC_GFX_CLK>,
+				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+			clock-names = "core",
+				"iface",
+				"rbbmtimer",
+				"mem",
+				"mem_iface";
+
+			power-domains = <&mmcc GPU_GDSC>;
+			iommus = <&adreno_smmu 0>;
+
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
+			qcom,gpu-quirk-two-pass-use-wfi;
+			qcom,gpu-quirk-fault-detect-mask;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			gpu_opp_table: opp-table {
+				compatible  ="operating-points-v2";
+
+				/*
+				 * 624Mhz and 560Mhz are only available on speed
+				 * bin (1 << 0). All the rest are available on
+				 * all bins of the hardware
+				 */
+				opp-624000000 {
+					opp-hz = /bits/ 64 <624000000>;
+					opp-supported-hw = <0x01>;
+				};
+				opp-560000000 {
+					opp-hz = /bits/ 64 <560000000>;
+					opp-supported-hw = <0x01>;
+				};
+				opp-510000000 {
+					opp-hz = /bits/ 64 <510000000>;
+					opp-supported-hw = <0xFF>;
+				};
+				opp-401800000 {
+					opp-hz = /bits/ 64 <401800000>;
+					opp-supported-hw = <0xFF>;
+				};
+				opp-315000000 {
+					opp-hz = /bits/ 64 <315000000>;
+					opp-supported-hw = <0xFF>;
+				};
+				opp-214000000 {
+					opp-hz = /bits/ 64 <214000000>;
+					opp-supported-hw = <0xFF>;
+				};
+				opp-133000000 {
+					opp-hz = /bits/ 64 <133000000>;
+					opp-supported-hw = <0xFF>;
+				};
+			};
+
+			zap-shader {
+				memory-region = <&zap_shader_region>;
+			};
+		};
+
 		mdss: mdss@900000 {
 			compatible = "qcom,mdss";
 
-- 
2.7.4

Re: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Vivek Gautam]

Hi,

On Wed, Jan 30, 2019 at 5:29 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Add an initial node for the Adreno GPU and it's companion
> SMMU.

The SMMU node is in another patch, so may be change the title of this
patch and update the commit text too?

>
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

[snip]

Regards
Vivek

Vivek

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Srinivas Kandagatla]

Thanks Vivek,

On 30/01/2019 05:32, Vivek Gautam wrote:
> Hi,
> 
> On Wed, Jan 30, 2019 at 5:29 AM Jordan Crouse<jcrouse@codeaurora.org>  wrote:
>> Add an initial node for the Adreno GPU and it's companion
>> SMMU.
> The SMMU node is in another patch, so may be change the title of this
> patch and update the commit text too?
> 

I will update this and send v2 of the series!

--srini

[PATCH 5/6] arm64: dts: apq8096-db820c: Add HDMI display support

[Srinivas Kandagatla]

From: Archit Taneja <architt@codeaurora.org>

The APQ8096 DB820c platform provides HDMI output. The MDSS block on
8x96 supports a direct HDMI out. Populate the MDSS, MDP and HDMI DT
nodes. Also, add the HDMI HPD and DDC pinctrl nodes with the bias
and driver strength specified for this platform.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 .../boot/dts/qcom/apq8096-db820c-pins.dtsi    | 52 +++++++++++++++++++
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi  | 27 ++++++++++
 2 files changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
index 6a573875d45a..1c0d06f59d00 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
@@ -62,4 +62,56 @@
 			bias-disable;
 		};
 	};
+
+	hdmi_hpd_active: hdmi_hpd_active {
+		mux {
+			pins = "gpio34";
+			function = "hdmi_hot";
+		};
+
+		config {
+			pins = "gpio34";
+			bias-pull-down;
+			drive-strength = <16>;
+		};
+	};
+
+	hdmi_hpd_suspend: hdmi_hpd_suspend {
+		mux {
+			pins = "gpio34";
+			function = "hdmi_hot";
+		};
+
+		config {
+			pins = "gpio34";
+			bias-pull-down;
+			drive-strength = <2>;
+		};
+	};
+
+	hdmi_ddc_active: hdmi_ddc_active {
+		mux {
+			pins = "gpio32", "gpio33";
+			function = "hdmi_ddc";
+		};
+
+		config {
+			pins = "gpio32", "gpio33";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	hdmi_ddc_suspend: hdmi_ddc_suspend {
+		mux {
+			pins = "gpio32", "gpio33";
+			function = "hdmi_ddc";
+		};
+
+		config {
+			pins = "gpio32", "gpio33";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 6d50449fbcdf..1e78f0b47c89 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -452,6 +452,33 @@
 				perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
 			};
 		};
+
+		mdss@900000 {
+			status = "okay";
+
+			mdp@901000 {
+				status = "okay";
+			};
+
+			hdmi-phy@9a0600 {
+				status = "okay";
+
+				vddio-supply = <&pm8994_l12>;
+				vcca-supply = <&pm8994_l28>;
+				#phy-cells = <0>;
+			};
+
+			hdmi-tx@9a0000 {
+				status = "okay";
+
+				pinctrl-names = "default", "sleep";
+				pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+				pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+
+				core-vdda-supply = <&pm8994_l12>;
+				core-vcc-supply = <&pm8994_s4>;
+			};
+		};
 	};
 
 
-- 
2.20.1

[PATCH 6/6] arm64: dts: db820c: Add sound card support

[Srinivas Kandagatla]

This patch adds support both digital and analog audio on DB820c.
This board has HDMI port and 3.5mm audio jack to support both digital
and analog audio respectively.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 .../dts/qcom/apq8096-db820c-pmic-pins.dtsi    |   9 ++
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi  |  98 ++++++++++++
 arch/arm64/boot/dts/qcom/msm8996-pins.dtsi    |  46 ++++++
 arch/arm64/boot/dts/qcom/msm8996.dtsi         | 140 ++++++++++++++++++
 4 files changed, 293 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index a6ad3d7fe655..7c5045949c01 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -36,6 +36,15 @@
 		};
 	};
 
+
+	audio_mclk: clk_div1 {
+		pinconf {
+			pins = "gpio15";
+			function = "func1";
+			power-source = <PM8994_GPIO_S4>; // 1.8V
+		};
+	};
+
 	volume_up_gpio: pm8996_gpio2 {
 		pinconf {
 			pins = "gpio2";
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 1e78f0b47c89..56f78405587e 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -18,6 +18,8 @@
 #include "apq8096-db820c-pmic-pins.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
 
 /*
  * GPIO name legend: proper name = the GPIO line is used as GPIO
@@ -63,6 +65,7 @@
 	};
 
 	clocks {
+		compatible = "simple-bus";
 		divclk4: divclk4 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -72,6 +75,15 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&divclk4_pin_a>;
 		};
+
+		div1_mclk: divclk1 {
+			compatible = "gpio-gate-clock";
+			pinctrl-0 = <&audio_mclk>;
+			pinctrl-names = "default";
+			clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+			#clock-cells = <0>;
+			enable-gpios = <&pm8994_gpios 15 0>;
+		};
 	};
 
 	soc {
@@ -453,6 +465,16 @@
 			};
 		};
 
+		slim_msm: slim@91c0000 {
+			ngd@1 {
+				wcd9335: codec@1{
+					clock-names = "mclk", "slimbus";
+					clocks = <&div1_mclk>,
+						 <&rpmcc RPM_SMD_BB_CLK1>;
+				};
+			};
+		};
+
 		mdss@900000 {
 			status = "okay";
 
@@ -479,6 +501,10 @@
 				core-vcc-supply = <&pm8994_s4>;
 			};
 		};
+
+		remoteproc@2080000 {
+			status = "okay";
+		};
 	};
 
 
@@ -666,3 +692,75 @@
 		};
 	};
 };
+
+&sound {
+	compatible = "qcom,apq8096-sndcard";
+	model = "DB820c";
+	audio-routing =	"RX_BIAS", "MCLK";
+
+	mm1-dai-link {
+		link-name = "MultiMedia1";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
+		};
+	};
+
+	mm2-dai-link {
+		link-name = "MultiMedia2";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
+		};
+	};
+
+	mm3-dai-link {
+		link-name = "MultiMedia3";
+		cpu {
+			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
+		};
+	};
+
+	hdmi-dai-link {
+		link-name = "HDMI";
+		cpu {
+			sound-dai = <&q6afedai HDMI_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&hdmi 0>;
+		};
+	};
+
+	slim-dai-link {
+		link-name = "SLIM Playback";
+		cpu {
+			sound-dai = <&q6afedai SLIMBUS_6_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&wcd9335 6>;
+		};
+	};
+
+	slimcap-dai-link {
+		link-name = "SLIM Capture";
+		cpu {
+			sound-dai = <&q6afedai SLIMBUS_0_TX>;
+		};
+
+		platform {
+			sound-dai = <&q6routing>;
+		};
+
+		codec {
+			sound-dai = <&wcd9335 1>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
index 131878db9852..c7ae88100cb6 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -13,6 +13,52 @@
 
 &msmgpio {
 
+		wcd9xxx_intr {
+			wcd_intr_default: wcd_intr_default{
+				mux {
+					pins = "gpio54";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio54";
+					drive-strength = <2>; /* 2 mA */
+					bias-pull-down; /* pull down */
+					input-enable;
+				};
+			};
+		};
+
+
+		cdc_reset_ctrl {
+			cdc_reset_sleep: cdc_reset_sleep {
+				mux {
+					pins = "gpio64";
+					function = "gpio";
+				};
+				config {
+					pins = "gpio64";
+					drive-strength = <16>;
+					bias-disable;
+					output-low;
+				};
+			};
+			cdc_reset_active:cdc_reset_active {
+				mux {
+					pins = "gpio64";
+					function = "gpio";
+				};
+				config {
+					pins = "gpio64";
+					drive-strength = <16>;
+					bias-pull-down;
+					output-high;
+				};
+			};
+		};
+
+
+
 	blsp1_spi0_default: blsp1_spi0_default {
 		pinmux {
 			function = "blsp_spi1";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index b5f23594905c..3c8e1eac8758 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/soc/qcom,apr.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -1178,6 +1179,33 @@
 			power-domains = <&mmcc MDSS_GDSC>;
 		};
 
+		lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
+			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+			reg = <0x1600000 0x20000>;
+			#iommu-cells = <1>;
+			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
+
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
+				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
+			clock-names = "iface", "bus";
+                        status = "okay";
+		};
+
 		agnoc@0 {
 			power-domains = <&gcc AGGRE0_NOC_GDSC>;
 			compatible = "simple-pm-bus";
@@ -1344,6 +1372,66 @@
 			};
 		};
 
+		slimbam:dma@9184000
+		{
+			compatible = "qcom,bam-v1.7.0";
+			qcom,controlled-remotely;
+			reg = <0x9184000 0x32000>;
+			num-channels  = <31>;
+			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <1>;
+			qcom,num-ees = <2>;
+		};
+
+		slim_msm: slim@91c0000 {
+			compatible = "qcom,slim-ngd-v1.5.0";
+			reg = <0x91c0000 0x2C000>;
+			reg-names = "ctrl";
+			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
+			dmas =	<&slimbam 3>, <&slimbam 4>,
+				<&slimbam 5>, <&slimbam 6>;
+			dma-names = "rx", "tx", "tx2", "rx2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ngd@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				tasha_ifd: tas-ifd {
+					compatible = "slim217,1a0";
+					reg  = <0 0>;
+				};
+
+				wcd9335: codec@1{
+					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
+					pinctrl-names = "default";
+
+					compatible = "slim217,1a0";
+					reg  = <1 0>;
+
+					interrupt-parent = <&msmgpio>;
+					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
+						     <53 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-names  = "intr1", "intr2";
+					interrupt-controller;
+					#interrupt-cells = <1>;
+					reset-gpios = <&msmgpio 64 0>;
+
+					slim-ifc-dev  = <&tasha_ifd>;
+
+					vdd-buck-supply = <&pm8994_s4>;
+					vdd-buck-sido-supply = <&pm8994_s4>;
+					vdd-tx-supply = <&pm8994_s4>;
+					vdd-rx-supply = <&pm8994_s4>;
+					vdd-io-supply = <&pm8994_s4>;
+
+					#sound-dai-cells = <1>;
+				};
+			};
+		};
+
 		gpu@b00000 {
 			compatible = "qcom,adreno-530.2", "qcom,adreno";
 			#stream-id-cells = <16>;
@@ -1473,6 +1561,7 @@
 
 				phys = <&hdmi_phy>;
 				phy-names = "hdmi_phy";
+				#sound-dai-cells = <1>;
 
 				ports {
 					#address-cells = <1>;
@@ -1511,6 +1600,9 @@
 		};
 	};
 
+	sound: sound {
+	};
+
 	adsp-pil {
 		compatible = "qcom,msm8996-adsp-pil";
 
@@ -1537,6 +1629,54 @@
 			mboxes = <&apcs_glb 8>;
 			qcom,smd-edge = <1>;
 			qcom,remote-pid = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			apr {
+				power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
+				compatible = "qcom,apr-v2";
+				qcom,smd-channels = "apr_audio_svc";
+				reg = <APR_DOMAIN_ADSP>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				q6core {
+					reg = <APR_SVC_ADSP_CORE>;
+					compatible = "qcom,q6core";
+				};
+
+				q6afe: q6afe {
+					compatible = "qcom,q6afe";
+					reg = <APR_SVC_AFE>;
+					q6afedai: dais {
+						compatible = "qcom,q6afe-dais";
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#sound-dai-cells = <1>;
+						hdmi@1 {
+							reg = <1>;
+						};
+					};
+				};
+
+				q6asm: q6asm {
+					compatible = "qcom,q6asm";
+					reg = <APR_SVC_ASM>;
+					q6asmdai: dais {
+						compatible = "qcom,q6asm-dais";
+						#sound-dai-cells = <1>;
+						iommus = <&lpass_q6_smmu 1>;
+					};
+				};
+
+				q6adm: q6adm {
+					compatible = "qcom,q6adm";
+					reg = <APR_SVC_ADM>;
+					q6routing: routing {
+						compatible = "qcom,q6adm-routing";
+						#sound-dai-cells = <0>;
+					};
+				};
+			};
 		};
 	};
 
-- 
2.20.1

[PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Jordan Crouse]

Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 +++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index a3a4dee..4108f21 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -473,6 +473,84 @@
 			};
 		};
 
+		adreno_smmu: arm,smmu@b40000 {
+			compatible = "arm,smmu-v2";
+			reg = <0xb40000 0x10000>;
+
+			#global-interrupts = <1>;
+			interrupts = <0 334 0>,
+				     <0 329 0>,
+				     <0 330 0>;
+			#iommu-cells = <1>;
+
+			clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
+				<&mmcc MMSS_MMAGIC_CFG_AHB_CLK>,
+				<&mmcc GPU_AHB_CLK>,
+				<&gcc GCC_MMSS_BIMC_GFX_CLK>,
+				<&gcc GCC_BIMC_GFX_CLK>,
+				<&mmcc MMSS_MISC_AHB_CLK>;
+			clock-names = "mmagic_ahb_clk",
+				"mmagic_cfg_ahb_clk",
+				"gpu_ahb_clk",
+				"gcc_mmss_bimc_gfx_clk",
+				"gcc_bimc_gfx_clk",
+				"mmss_misc_bus_clk";
+
+			power-domains = <&mmcc GPU_GDSC>;
+
+			qcom,skip-init;
+			qcom,register-save;
+
+			status = "okay";
+		};
+
+		adreno-3xx@b00000 {
+			compatible = "qcom,adreno-3xx";
+			#stream-id-cells = <16>;
+
+			reg = <0xb00000 0x3f000>;
+			reg-names = "kgsl_3d0_reg_memory";
+
+			interrupts = <0 300 0>;
+			interrupt-names = "kgsl_3d0_irq";
+
+			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+				<&mmcc GPU_AHB_CLK>,
+				<&mmcc GPU_GX_RBBMTIMER_CLK>,
+				<&gcc GCC_BIMC_GFX_CLK>,
+				<&gcc GCC_MMSS_BIMC_GFX_CLK>,
+				<&mmcc MMSS_MMAGIC_AHB_CLK>;
+
+			clock-names = "core_clk",
+				"iface_clk",
+				"rbbmtimer_clk",
+				"mem_clk",
+				"mem_iface_clk",
+				"alt_mem_iface_clk";
+
+			power-domains = <&mmcc GPU_GDSC>;
+			iommus = <&adreno_smmu 0>;
+
+			/* There are patchlevel 3 chips in the world (Snapdragon
+			 * (820) but they are functionally similar to the 821 in
+			 * the code so we can safely set the chipset as
+			 * patchlevel 4. */
+			qcom,chipid = <0x05030004>;
+
+			/* This is a safe speed for bring up in all bin levels.
+			 * This isn't the fastest the chip can go, but we can
+			 * get there eventually */
+			qcom,gpu-pwrlevels {
+				compatible = "qcom,gpu-pwrlevels";
+				qcom,gpu-pwrlevel@0 {
+					qcom,gpu-freq = <205000000>;
+				};
+				qcom,gpu-pwrlevel@1 {
+					qcom,gpu-freq = <27000000>;
+				};
+			};
+		};
+
 		mdp_smmu: arm,smmu@d00000 {
 			compatible = "arm,smmu-v2";
 			reg = <0xd00000 0x10000>;
-- 
1.9.1

_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

[Stephen Boyd]

On 12/02/2016 07:30 AM, Jordan Crouse wrote:
> Add an initial node for the Adreno GPU and it's companion
> SMMU. The GPU node is mostly complete except for a bare
> bones power table that will be filled out more completely
> later.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---

Hm.. I see that I missed the 8064 dts update and Andy has already
applied it. Sigh.

>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 +++++++++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index a3a4dee..4108f21 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -473,6 +473,84 @@
>  			};
>  		};
>  
> +		adreno_smmu: arm,smmu@b40000 {

iommu@b40000 ?

> +			compatible = "arm,smmu-v2";
> +			reg = <0xb40000 0x10000>;
> +
> +			#global-interrupts = <1>;
> +			interrupts = <0 334 0>,
> +				     <0 329 0>,
> +				     <0 330 0>;

We're using the pretty macros now for GIC_SPI and irq triggers. Please
add them on interrupts.

> +			#iommu-cells = <1>;
> +
> +			clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
> +				<&mmcc MMSS_MMAGIC_CFG_AHB_CLK>,
> +				<&mmcc GPU_AHB_CLK>,
> +				<&gcc GCC_MMSS_BIMC_GFX_CLK>,
> +				<&gcc GCC_BIMC_GFX_CLK>,
> +				<&mmcc MMSS_MISC_AHB_CLK>;
> +			clock-names = "mmagic_ahb_clk",
> +				"mmagic_cfg_ahb_clk",
> +				"gpu_ahb_clk",
> +				"gcc_mmss_bimc_gfx_clk",
> +				"gcc_bimc_gfx_clk",
> +				"mmss_misc_bus_clk";

Please remove _clk from all clock names as it's redundant.

> +
> +			power-domains = <&mmcc GPU_GDSC>;
> +
> +			qcom,skip-init;
> +			qcom,register-save;
> +
> +			status = "okay";

We don't need status = "okay" here. Typically those are just in the
board files.

> +		};
> +
> +		adreno-3xx@b00000 {

gpu@b00000 ?

> +			compatible = "qcom,adreno-3xx";
> +			#stream-id-cells = <16>;
> +
> +			reg = <0xb00000 0x3f000>;
> +			reg-names = "kgsl_3d0_reg_memory";
> +
> +			interrupts = <0 300 0>;
> +			interrupt-names = "kgsl_3d0_irq";
> +
> +			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
> +				<&mmcc GPU_AHB_CLK>,
> +				<&mmcc GPU_GX_RBBMTIMER_CLK>,
> +				<&gcc GCC_BIMC_GFX_CLK>,
> +				<&gcc GCC_MMSS_BIMC_GFX_CLK>,
> +				<&mmcc MMSS_MMAGIC_AHB_CLK>;
> +
> +			clock-names = "core_clk",
> +				"iface_clk",
> +				"rbbmtimer_clk",
> +				"mem_clk",
> +				"mem_iface_clk",
> +				"alt_mem_iface_clk";

Is there a binding update for new clock names? I haven't seen it. Sad
that we couldn't remove _clk from the names here like everywhere else.

> +
> +			power-domains = <&mmcc GPU_GDSC>;
> +			iommus = <&adreno_smmu 0>;
> +
> +			/* There are patchlevel 3 chips in the world (Snapdragon
> +			 * (820) but they are functionally similar to the 821 in
> +			 * the code so we can safely set the chipset as
> +			 * patchlevel 4. */
> +			qcom,chipid = <0x05030004>;
> +
> +			/* This is a safe speed for bring up in all bin levels.
> +			 * This isn't the fastest the chip can go, but we can
> +			 * get there eventually */
> +			qcom,gpu-pwrlevels {
> +				compatible = "qcom,gpu-pwrlevels";
> +				qcom,gpu-pwrlevel@0 {
> +					qcom,gpu-freq = <205000000>;
> +				};
> +				qcom,gpu-pwrlevel@1 {
> +					qcom,gpu-freq = <27000000>;
> +				};
> +			};

These should be OPPs.

> +		};
> +
>  		mdp_smmu: arm,smmu@d00000 {
>  			compatible = "arm,smmu-v2";
>  			reg = <0xd00000 0x10000>;


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