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Tue, 09 Dec 2025 01:02:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkhI1GXHBiPquCji+ZgoLgAwuwKObWbNekX0HnKK5pPxwDFhYjZRIriYLSQ5ETb888EDm3lQ== X-Received: by 2002:a17:902:f78b:b0:295:55fc:67a0 with SMTP id d9443c01a7336-29ea02a9cb2mr8870475ad.2.1765270956300; Tue, 09 Dec 2025 01:02:36 -0800 (PST) Received: from [10.206.101.67] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29e2444f5a0sm69951955ad.33.2025.12.09.01.02.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 01:02:35 -0800 (PST) Message-ID: <157a3960-0110-4026-8ef5-e3378c8db693@oss.qualcomm.com> Date: Tue, 9 Dec 2025 14:32:29 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/6] media: iris: Introduce vpu ops for vpu4 with necessary hooks To: Bryan O'Donoghue , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Dmitry Baryshkov , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy References: <20251107-knp_video-v3-0-50c86cbb0eb8@oss.qualcomm.com> <20251107-knp_video-v3-6-50c86cbb0eb8@oss.qualcomm.com> <5a5908db-aa96-4cfa-a908-d393dd2d79c0@kernel.org> Content-Language: en-US From: Vikash Garodia In-Reply-To: <5a5908db-aa96-4cfa-a908-d393dd2d79c0@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=dKarWeZb c=1 sm=1 tr=0 ts=6937e5ad cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=nqpN-pjiYS0InRIFTCgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: 5KSUO9c71ew6aeqOF9YP0hgP1HpYcpuL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA5MDA2MyBTYWx0ZWRfXwN/bWkolMgrF +U01CcHYLqfT0JATP0q0lMtdaVwD5dj1izqbb58RnlDDAKBI6DURwxwqugMAHzeTVJ/zmMTnF/A qct+xz9bdZnXcpGr+P0uhSaf94hGwD9pKGhHfCRRMLszXShuGM3xYJGNCFH4N/Olo9CYI5aSQya utZN+JJ4ZERgKA6j25+xGu7G5LQPypAP2Mifz8M9MAw3LrWJGJ8XamLx40YsbxfZ/YkBVEKyZB6 dkq79zoxGmpUBCO5KznGCY2JTxq85HW7Oiu8oSQMlToXVO2PgNmV9j91tHxmUtpP/ZgSSbTQ0RF nWaSdpxohkAwjFAhfwY2iompqYAkxXiesRlGrplyx5szY6KAZvTss2fOSqJg4vr4khvEv5qX6dx 1XUqM+goVMMxxAF51MBImB54GXaslA== X-Proofpoint-GUID: 5KSUO9c71ew6aeqOF9YP0hgP1HpYcpuL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-09_02,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 priorityscore=1501 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512090063 On 12/7/2025 4:34 AM, Bryan O'Donoghue wrote: > On 07/11/2025 09:49, Vikash Garodia wrote: >> Add power sequence for vpu4 by reusing from previous generation wherever >> possible. Hook up vpu4 op with vpu4 specific implemtation or resue from >> earlier generation wherever feasible, like clock calculation in this >> case. >> >> Co-developed-by: Vishnu Reddy >> Signed-off-by: Vishnu Reddy >> Signed-off-by: Vikash Garodia >> --- > >> +static void iris_vpu4x_power_off_hardware(struct iris_core *core) >> +{ >> +    u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); >> +    bool handshake_done, handshake_busy; >> +    u32 value, count = 0; >> + >> +    iris_vpu4x_genpd_set_hwmode(core, false, efuse_value); >> + >> +    if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) >> +        iris_vpu4x_power_off_apv(core); >> + >> +    value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); >> + >> +    if (!(value & CORE_PWR_ON)) >> +        goto disable_clocks_and_power; >> + >> +    value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >> + >> +    if (value & CORE_CLK_HALT) >> +        writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >> + >> +    readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value, >> +               value & VPU_IDLE_BITS, 2000, 20000); >> + >> +    do { >> +        writel(REQ_POWER_DOWN_PREP, core->reg_base + >> AON_WRAPPER_MVP_NOC_LPI_CONTROL); >> +        usleep_range(10, 20); >> +        value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); >> + >> +        handshake_done = value & NOC_LPI_STATUS_DONE; >> +        handshake_busy = value & (NOC_LPI_STATUS_DENY | >> NOC_LPI_STATUS_ACTIVE); >> + >> +        if (handshake_done || !handshake_busy) >> +            break; >> + >> +        writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >> +        usleep_range(10, 20); >> + >> +    } while (++count < 1000); >> + >> +    if (!handshake_done && handshake_busy) >> +        dev_err(core->dev, "LPI handshake timeout\n"); >> + >> +    writel(MVP_NOC_RESET_REQ_MASK, core->reg_base + >> AON_WRAPPER_MVP_NOC_RESET_REQ); >> +    readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, >> +               value, value == MVP_NOC_RESET_REQ_MASK, 200, 2000); > > I realise it replicates what we already have upstream but... > > if (!handshake_done && etc) is true then how does it make sense to > continue on with the routine at all ? Yes, LPI (low power..) is an optional "good to have" routine before resetting the NOC and powering down. > > We would expect the poll_timeout to timeout .. ? during good times, it would not, and when it times out, it is always good to force reset the NOC before the GDSCs/clocks are turned off. > > If the documentation states loop 1000 times trying this then does it > also say continue to try to power things off if that 1000 retries fails ? Thats correct. > > I realise its a nit-pick but the logic seems a bit fluffy here. Could > you tidy it up ? > > Also now that I look at it - vpu2 and vpu3 both trap the timeout and > jump to some kind of cleanup routine. > > goto disable_power; > > Why is that logic not being followed here ? > >> +    writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST); >> +    writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); >> +    readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, >> +               value, value == 0x0, 200, 2000); > > Feels like there is little point in having a poll timeout if we throw > away a timeout result code.. > > Not sure why you're changing up the logic from previous versions ? > Given the NOC reset/ack is recommended, even if LPI times out, we can move to disable_power i.e power off clocks/GDSCs, once NOC reset times out. Regards, Vikash