Re: [PATCH 2/4] drm/msm: dsi: Use OPP API to set clk/perf state

Rajendra Nayak
2020-07-02T08:55:40Z

On 7/1/2020 9:57 PM, Matthias Kaehlcke wrote:
> On Tue, Jun 30, 2020 at 05:26:14PM +0530, Rajendra Nayak wrote:
>> On SDM845 DSI needs to express a perforamnce state
>
> nit: performance
>
>> requirement on a power domain depending on the clock rates.
>> Use OPP table from DT to register with OPP framework and use
>> dev_pm_opp_set_rate() to set the clk/perf state.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> ---
>> drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
>> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +--
>> drivers/gpu/drm/msm/dsi/dsi_host.c | 58 ++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 62 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
>> index 4de771d..ba7583c 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
>> @@ -180,10 +180,12 @@ int msm_dsi_runtime_suspend(struct device *dev);
>> int msm_dsi_runtime_resume(struct device *dev);
>> int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host);
>> int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host);
>> +int dsi_link_clk_set_rate_6g_v2(struct msm_dsi_host *msm_host);
>> int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
>> int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
>> void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);
>> void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host);
>> +void dsi_link_clk_disable_6g_v2(struct msm_dsi_host *msm_host);
>> int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size);
>> int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size);
>> void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host);
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> index 813d69d..773c4fe 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> @@ -210,9 +210,9 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
>> };
>>
>> static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
>> - .link_clk_set_rate = dsi_link_clk_set_rate_6g,
>> + .link_clk_set_rate = dsi_link_clk_set_rate_6g_v2,
>> .link_clk_enable = dsi_link_clk_enable_6g,
>> - .link_clk_disable = dsi_link_clk_disable_6g,
>> + .link_clk_disable = dsi_link_clk_disable_6g_v2,
>> .clk_init_ver = dsi_clk_init_6g_v2,
>> .tx_buf_alloc = dsi_tx_buf_alloc_6g,
>> .tx_buf_get = dsi_tx_buf_get_6g,
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 11ae5b8..890531c 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -14,6 +14,7 @@
>> #include <linux/of_graph.h>
>> #include <linux/of_irq.h>
>> #include <linux/pinctrl/consumer.h>
>> +#include <linux/pm_opp.h>
>> #include <linux/regmap.h>
>> #include <linux/regulator/consumer.h>
>> #include <linux/spinlock.h>
>> @@ -111,6 +112,9 @@ struct msm_dsi_host {
>> struct clk *pixel_clk_src;
>> struct clk *byte_intf_clk;
>>
>> + struct opp_table *opp_table;
>> + bool has_opp_table;
>> +
>> u32 byte_clk_rate;
>> u32 pixel_clk_rate;
>> u32 esc_clk_rate;
>> @@ -537,6 +541,38 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
>> return 0;
>> }
>>
>> +int dsi_link_clk_set_rate_6g_v2(struct msm_dsi_host *msm_host)
>> +{
>> + int ret;
>> + struct device *dev = &msm_host->pdev->dev;
>> +
>> + DBG("Set clk rates: pclk=%d, byteclk=%d",
>> + msm_host->mode->clock, msm_host->byte_clk_rate);
>> +
>> + ret = dev_pm_opp_set_rate(dev, msm_host->byte_clk_rate);
>> + if (ret) {
>> + pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
>> + return ret;
>> + }
>> +
>> + ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
>> + if (ret) {
>> + pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
>> + return ret;
>> + }
>> +
>> + if (msm_host->byte_intf_clk) {
>> + ret = clk_set_rate(msm_host->byte_intf_clk,
>> + msm_host->byte_clk_rate / 2);
>> + if (ret) {
>> + pr_err("%s: Failed to set rate byte intf clk, %d\n",
>> + __func__, ret);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>
> xThis function is essentially the same as dsi_link_clk_set_rate_6g(),
> except for the use of dev_pm_opp_set_rate() instead of clk_set_rate().
>
> IIUC dev_pm_opp_set_rate() just calls clk_set_rate() if the device has
> no OPP table. If that's correct you could just call dev_pm_opp_set_rate()
> in dsi_link_clk_set_rate_6g().
>
> /*
> * For IO devices which require an OPP on some platforms/SoCs
> * while just needing to scale the clock on some others
> * we look for empty OPP tables with just a clock handle and
> * scale only the clk. This makes dev_pm_opp_set_rate()
> * equivalent to a clk_set_rate()
> */
> if (!_get_opp_count(opp_table)) {
> ret = _generic_set_opp_clk_only(dev, clk, freq);
> goto put_opp_table;
> }

ah, thats right, I think I had this code from before that support got
added to dev_pm_opp_set_rate() and I just did not update this driver to
make use of it. Thanks for catching it, I will fix it up and repost soon.

>
> https://elixir.bootlin.com/linux/v5.7.6/source/drivers/opp/core.c#L855
>
>> int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
>> {
>> @@ -665,6 +701,13 @@ void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
>> clk_disable_unprepare(msm_host->byte_clk);
>> }
>>
>> +void dsi_link_clk_disable_6g_v2(struct msm_dsi_host *msm_host)
>> +{
>> + /* Drop the performance state vote */
>> + dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
>
> Couldn't you just do this in dsi_link_clk_disable_6g() ?

yes, looks like I can, I'll get rid of both of these additional functions.

thanks,
Rajendra