From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC89E156C6A; Sat, 27 Apr 2024 19:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714246472; cv=none; b=KNY140Oyud6rAzNJDJ2zOEu9lDsH9Uvld/24yUZ7tmVIxINfHfpBp+xpxmOFvMCGdF+WFKo5YZLtFGjhQCwOYhrnQceyyHBZc7ZTqxraPRraGFYjvZp8+3niGF/hitUZcfctqYhPw6pT+/f+NoOXrOuJS/KeqrTS5FlyqwkpgTM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714246472; c=relaxed/simple; bh=U5xS1LWO8IquxiHUzUXPnIjhZdMQ7kUJxM1O1SIrCWg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NKDjmqq7kcKO9rgRcu1wzg3HrqyfFxTjqsKn/ysJvCLN7M1nK9rnxKJTXK7xXw+DGUXjgJaK3wG8Tart0bMSEU4musWSiAb7UgUcg8NXWIrf5ZKtSCsiUJRDjM5JCG7MUNsh/itrrEoxM7LTqZ+mx7+xyiQFHFcvQ8s2XBG4rB8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hhoZD+/u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hhoZD+/u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 888D1C32781; Sat, 27 Apr 2024 19:34:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714246472; bh=U5xS1LWO8IquxiHUzUXPnIjhZdMQ7kUJxM1O1SIrCWg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hhoZD+/ugEBWKlZy/mAUL9KXh2IH1BbuTEfaayAaWw+eJGuh5QoKQNCcj5wpbAeHq FoX95e9TEvXYZYWOZ3nkwKsY7xrkfpc1b0P8QJ8iR1zWIpID/NGrdljck2fpzDRqgk /iCJD5JAGSNvwtoRgWx4/T8npw/gtRXKhJcUdQkaPCDnSvDwYWyqLEHvSWwZoDnloR F3xuMSyUAh/36ZHE2eEIqC9+JCN3gzUFhoioH23WfWdtR/RBzzkKL4u0t6EpkwEWmD 6wR/PPo7W/kQq+OXzFJadfjDRExANNAUgR56x5ToJjFX+ZvPeWdL4TI4uhVGedskqI ZS3+c+F1yBXJg== From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Vinod Koul , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Subject: Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src Date: Sat, 27 Apr 2024 14:34:21 -0500 Message-ID: <171424646112.1448451.8203210233277643102.b4-ty@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240427-topic-8450sdc2-v1-1-631cbb59e0e5@linaro.org> References: <20240427-topic-8450sdc2-v1-1-631cbb59e0e5@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Sat, 27 Apr 2024 14:01:07 +0200, Konrad Dybcio wrote: > Similar to how it works on other SoCs, the top frequency of the SDHCI2 > core clock is generated by a separate PLL (peculiar design choice) that > is not guaranteed to be enabled (why does the clock framework not handle > this by default?). > > Add the CLK_OPS_PARENT_ENABLE flag to make sure we're not muxing the > RCG input to a dormant source. > > [...] Applied, thanks! [1/1] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src commit: 2ee7aabf9e25628c7bd17ed650cac84419d12eb1 Best regards, -- Bjorn Andersson