[PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[Taniya Das]

Add the video, camera, display and gpu clock controller nodes and the
cpufreq-hw node to support cpu scaling.

Clock Dependency:
https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com

Changes in v5:
- Update the documentation for CPUFREQ-HW for QCS615.
- Update the device tree node for cpufreq-hw to point to the new compatible.
- Link to v4: https://lore.kernel.org/r/20250625-qcs615-mm-cpu-dt-v4-v4-0-9ca880c53560@quicinc.com

Changes in v4:
- Fix the typo(removal of "") from cpufreq-hw node
- Link to v3: https://lore.kernel.org/r/20250612-qcs615-mm-cpu-dt-v3-v3-0-721d5db70342@quicinc.com

Changes in v3:
- Move the cpufreq-hw node under /soc {}
- Add the RB-tag on (v2) from [Konrad]

Changes in v2:
- pad address field to 8 digits [Dmitry]
- Replace cpu/CPU in commit [Dmitry]
- Update the binding to use SC7180 compatible, as QCS615 uses the same
  hardware version.
- Link to v1: https://lore.kernel.org/r/20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
Taniya Das (3):
      dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible
      arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock
      arm64: dts: qcom: qcs615: Add CPU scaling clock node

 .../bindings/cpufreq/cpufreq-qcom-hw.yaml          |  2 +
 arch/arm64/boot/dts/qcom/qcs615.dtsi               | 80 ++++++++++++++++++++++
 2 files changed, 82 insertions(+)
---
base-commit: 2ae2aaafb21454f4781c30734959cf223ab486ef
change-id: 20250625-qcs615-mm-cpu-dt-v4-b6b9bc7d3e56
prerequisite-message-id: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com>
prerequisite-patch-id: 9879d98848e0c7b1a5d898d657c8318738c44ac2
prerequisite-patch-id: 6414e91724ba90fe820c3d2bb5caa720c99cf3be
prerequisite-patch-id: e4e24f3dc507891b70936c9587ee1416f1a53e6f
prerequisite-patch-id: 23062409b23977940c958bf22a215ae5dc45e93a
prerequisite-patch-id: c35335d37fdf9a7f665f1c6d79d34b091d45e291
prerequisite-patch-id: 9a0caaaa8d25634dd0db5edffbc939eb7e734c6c
prerequisite-patch-id: 0b08c5ea612ac291dd829f5e7e63c499cd2812f7
prerequisite-patch-id: 2327271def3656283d53dadb2ce9f8cd561249d1
prerequisite-patch-id: c97840c551e081b0b9bf6c0e77b551935454f62d
prerequisite-patch-id: 71f0eb0fb98c3177dcbe6736c120cba4efef0c33

Best regards,
-- 
Taniya Das <quic_tdas@quicinc.com>

[PATCH v5 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible

[Taniya Das]

Document compatible for cpufreq hardware on Qualcomm QCS615 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index e0242bed33420a39b8a8cff4229ba9eee994ca30..2d42fc3d8ef811368c990977173f41b26535e0c8 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -22,6 +22,7 @@ properties:
         items:
           - enum:
               - qcom,qcm2290-cpufreq-hw
+              - qcom,qcs615-cpufreq-hw
               - qcom,sc7180-cpufreq-hw
               - qcom,sc8180x-cpufreq-hw
               - qcom,sdm670-cpufreq-hw
@@ -132,6 +133,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs615-cpufreq-hw
               - qcom,qdu1000-cpufreq-epss
               - qcom,sa8255p-cpufreq-epss
               - qcom,sa8775p-cpufreq-epss

-- 
2.34.1

[PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Taniya Das]

Add support for video, camera, display and gpu clock controller nodes
for QCS615 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83ceca331097ae37 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3,7 +3,11 @@
  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,qcs615-camcc.h>
+#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+#include <dt-bindings/clock/qcom,qcs615-videocc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
@@ -1506,6 +1510,18 @@ data-pins {
 			};
 		};
 
+		gpucc: clock-controller@5090000 {
+			compatible = "qcom,qcs615-gpucc";
+			reg = <0 0x05090000 0 0x9000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GPLL0>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		stm@6002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x06002000 0x0 0x1000>,
@@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		videocc: clock-controller@ab00000 {
+			compatible = "qcom,qcs615-videocc";
+			reg = <0 0x0ab00000 0 0x10000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ad00000 {
+			compatible = "qcom,qcs615-camcc";
+			reg = <0 0x0ad00000 0 0x10000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,qcs615-dispcc";
+			reg = <0 0x0af00000 0 0x20000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,qcs615-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,

-- 
2.34.1

[PATCH v5 3/3] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Taniya Das]

Add cpufreq-hw node to support CPU frequency scaling.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 5adf409d7ce7226042c759cc83ceca331097ae37..142338069a74cc6c263e17d84efa22ccd0c26813 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -36,6 +36,8 @@ cpu0: cpu@0 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_0>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 
 			l2_0: l2-cache {
@@ -56,6 +58,8 @@ cpu1: cpu@100 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_100>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_100: l2-cache {
 			      compatible = "cache";
@@ -75,6 +79,8 @@ cpu2: cpu@200 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_200>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_200: l2-cache {
 			      compatible = "cache";
@@ -94,6 +100,8 @@ cpu3: cpu@300 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_300>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_300: l2-cache {
 			      compatible = "cache";
@@ -113,6 +121,8 @@ cpu4: cpu@400 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_400>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_400: l2-cache {
 			      compatible = "cache";
@@ -132,6 +142,8 @@ cpu5: cpu@500 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_500>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_500: l2-cache {
 			      compatible = "cache";
@@ -151,6 +163,8 @@ cpu6: cpu@600 {
 			capacity-dmips-mhz = <1740>;
 			dynamic-power-coefficient = <404>;
 			next-level-cache = <&l2_600>;
+			clocks = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 
 			l2_600: l2-cache {
@@ -171,6 +185,8 @@ cpu7: cpu@700 {
 			capacity-dmips-mhz = <1740>;
 			dynamic-power-coefficient = <404>;
 			next-level-cache = <&l2_700>;
+			clocks = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 
 			l2_700: l2-cache {
 			      compatible = "cache";
@@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
 				qcom,remote-pid = <2>;
 			};
 		};
+
+		cpufreq_hw: cpufreq@18323000 {
+			compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw";
+			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
+			reg-names = "freq-domain0", "freq-domain1";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+
 	};
 
 	arch_timer: timer {

-- 
2.34.1

Re: [PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[Krzysztof Kozlowski]

On Wed, Jul 02, 2025 at 02:43:08PM +0530, Taniya Das wrote:
> Add the video, camera, display and gpu clock controller nodes and the
> cpufreq-hw node to support cpu scaling.
> 
> Clock Dependency:
> https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com
> 
> Changes in v5:
> - Update the documentation for CPUFREQ-HW for QCS615.

What did you update? This has to be specific, not vague.

Best regards,
Krzysztof

Re: [PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[Taniya Das]

On 7/3/2025 12:51 PM, Krzysztof Kozlowski wrote:
> On Wed, Jul 02, 2025 at 02:43:08PM +0530, Taniya Das wrote:
>> Add the video, camera, display and gpu clock controller nodes and the
>> cpufreq-hw node to support cpu scaling.
>>
>> Clock Dependency:
>> https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com
>>
>> Changes in v5:
>> - Update the documentation for CPUFREQ-HW for QCS615.
> 
> What did you update? This has to be specific, not vague.

Sorry, this is the update: "compatible for cpufreq hardware on Qualcomm
QCS615 platform."

-- Taniya

Re: [PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[Krzysztof Kozlowski]

On 03/07/2025 10:28, Taniya Das wrote:
> 
> 
> On 7/3/2025 12:51 PM, Krzysztof Kozlowski wrote:
>> On Wed, Jul 02, 2025 at 02:43:08PM +0530, Taniya Das wrote:
>>> Add the video, camera, display and gpu clock controller nodes and the
>>> cpufreq-hw node to support cpu scaling.
>>>
>>> Clock Dependency:
>>> https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com
>>>
>>> Changes in v5:
>>> - Update the documentation for CPUFREQ-HW for QCS615.
>>
>> What did you update? This has to be specific, not vague.
> 
> Sorry, this is the update: "compatible for cpufreq hardware on Qualcomm
> QCS615 platform."
> 
Do you mean you added a new patch?

Best regards,
Krzysztof

Re: [PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[Taniya Das]

On 7/3/2025 2:06 PM, Krzysztof Kozlowski wrote:
> On 03/07/2025 10:28, Taniya Das wrote:
>>
>>
>> On 7/3/2025 12:51 PM, Krzysztof Kozlowski wrote:
>>> On Wed, Jul 02, 2025 at 02:43:08PM +0530, Taniya Das wrote:
>>>> Add the video, camera, display and gpu clock controller nodes and the
>>>> cpufreq-hw node to support cpu scaling.
>>>>
>>>> Clock Dependency:
>>>> https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com
>>>>
>>>> Changes in v5:
>>>> - Update the documentation for CPUFREQ-HW for QCS615.
>>>
>>> What did you update? This has to be specific, not vague.
>>
>> Sorry, this is the update: "compatible for cpufreq hardware on Qualcomm
>> QCS615 platform."
>>
> Do you mean you added a new patch?
> 

Yes, Krzysztof, I’ve added a new patch. Initially, I was reusing the
compatible string of the SC7180 SoC for QCS615, since both SoCs share
the same hardware design. However, Dmitry and Konrad raised a valid
point — if we ever need to handle quirks specific to a particular SoC,
using distinct compatible entries would make that easier. Based on that,
I’ve updated the patch accordingly.

-- Taniya.

Re: [PATCH v5 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible

[Krzysztof Kozlowski]

On Wed, Jul 02, 2025 at 02:43:09PM +0530, Taniya Das wrote:
> Document compatible for cpufreq hardware on Qualcomm QCS615 platform.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v5 3/3] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Dmitry Baryshkov]

On Wed, Jul 02, 2025 at 02:43:11PM +0530, Taniya Das wrote:
> Add cpufreq-hw node to support CPU frequency scaling.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Konrad Dybcio]

On 7/2/25 11:13 AM, Taniya Das wrote:
> Add support for video, camera, display and gpu clock controller nodes
> for QCS615 platform.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---

Bjorn mentioned offline that these controllers should
probably have power-domains attached to them (perhaps bar
GPU_CC, that's under discussion..)

Konrad

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Akhil P Oommen]

On 7/30/2025 7:07 PM, Konrad Dybcio wrote:
> On 7/2/25 11:13 AM, Taniya Das wrote:
>> Add support for video, camera, display and gpu clock controller nodes
>> for QCS615 platform.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
> 
> Bjorn mentioned offline that these controllers should
> probably have power-domains attached to them (perhaps bar
> GPU_CC, that's under discussion..)

QCS615 has an rgmu which doesn't manage gpucc. So this is a different
case from the other discussion. Are we talking about scaling mx and cx
rail while setting clk rate? Downstream clk driver does that on behalf
of the clients. I suppose you are not talking about that here.

-Akhil.

> 
> Konrad
> 

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Taniya Das]

On 7/30/2025 7:07 PM, Konrad Dybcio wrote:
> On 7/2/25 11:13 AM, Taniya Das wrote:
>> Add support for video, camera, display and gpu clock controller nodes
>> for QCS615 platform.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
> 
> Bjorn mentioned offline that these controllers should
> probably have power-domains attached to them (perhaps bar
> GPU_CC, that's under discussion..)
> 
The GPU_CC on QCS615 is all on CX and we do not require any power-domain
to be attached.

-- Taniya.

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Konrad Dybcio]

On 7/30/25 6:10 PM, Akhil P Oommen wrote:
> On 7/30/2025 7:07 PM, Konrad Dybcio wrote:
>> On 7/2/25 11:13 AM, Taniya Das wrote:
>>> Add support for video, camera, display and gpu clock controller nodes
>>> for QCS615 platform.
>>>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>
>> Bjorn mentioned offline that these controllers should
>> probably have power-domains attached to them (perhaps bar
>> GPU_CC, that's under discussion..)
> 
> QCS615 has an rgmu which doesn't manage gpucc. So this is a different
> case from the other discussion. Are we talking about scaling mx and cx
> rail while setting clk rate? Downstream clk driver does that on behalf
> of the clients. I suppose you are not talking about that here.

This is also relevant, as pmdomain states are propagated up the
tree, e.g. if we have:

usb@foobar {
	...
	power-domains = <&gcc USB30_GDSC>;
};

when someone calls dev_pm_opp_set_level() (or something equivalent like
dev_pm_opp_set_rate() with required-opps defined in the table), it
will set the performance state of the GDSC (which is a NOP for the GDSC
itself), but if we have this hunk:

gcc@feedbeef {
	...
	power-domains = <&rpmhpd RPMHPD_CX>;
};

RPMHPD_CX will be declared as a parent of all GCC GDSCs and its state
will be altered too. See:

drivers/pmdomain/core.c : _genpd_set_performance_state()


TLDR: clients are responsible for ensuring vdd_levels are set

Konrad

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Bjorn Andersson]

On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
> Add support for video, camera, display and gpu clock controller nodes
> for QCS615 platform.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---

  DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
        from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
        from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
        from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
        from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
        from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#


The missing clock-names in clock-controller@100000 predates this series.
Sorry for merging broken patches in the past, please fix that as well.

Regards,
Bjorn

>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83ceca331097ae37 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -3,7 +3,11 @@
>   * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
> +#include <dt-bindings/clock/qcom,qcs615-camcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
>  #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
> +#include <dt-bindings/clock/qcom,qcs615-videocc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
>  #include <dt-bindings/interconnect/qcom,icc.h>
> @@ -1506,6 +1510,18 @@ data-pins {
>  			};
>  		};
>  
> +		gpucc: clock-controller@5090000 {
> +			compatible = "qcom,qcs615-gpucc";
> +			reg = <0 0x05090000 0 0x9000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GPLL0>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		stm@6002000 {
>  			compatible = "arm,coresight-stm", "arm,primecell";
>  			reg = <0x0 0x06002000 0x0 0x1000>,
> @@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		videocc: clock-controller@ab00000 {
> +			compatible = "qcom,qcs615-videocc";
> +			reg = <0 0x0ab00000 0 0x10000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&sleep_clk>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		camcc: clock-controller@ad00000 {
> +			compatible = "qcom,qcs615-camcc";
> +			reg = <0 0x0ad00000 0 0x10000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		dispcc: clock-controller@af00000 {
> +			compatible = "qcom,qcs615-dispcc";
> +			reg = <0 0x0af00000 0 0x20000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,qcs615-pdc", "qcom,pdc";
>  			reg = <0x0 0x0b220000 0x0 0x30000>,
> 
> -- 
> 2.34.1
> 

Re: [PATCH v5 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible

[Bjorn Andersson]

On Wed, Jul 02, 2025 at 02:43:09PM +0530, Taniya Das wrote:
> Document compatible for cpufreq hardware on Qualcomm QCS615 platform.
> 

@Viresh, @Rafael. Please merge this binding patch through your trees.

Regards,
Bjorn

> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> index e0242bed33420a39b8a8cff4229ba9eee994ca30..2d42fc3d8ef811368c990977173f41b26535e0c8 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> @@ -22,6 +22,7 @@ properties:
>          items:
>            - enum:
>                - qcom,qcm2290-cpufreq-hw
> +              - qcom,qcs615-cpufreq-hw
>                - qcom,sc7180-cpufreq-hw
>                - qcom,sc8180x-cpufreq-hw
>                - qcom,sdm670-cpufreq-hw
> @@ -132,6 +133,7 @@ allOf:
>          compatible:
>            contains:
>              enum:
> +              - qcom,qcs615-cpufreq-hw
>                - qcom,qdu1000-cpufreq-epss
>                - qcom,sa8255p-cpufreq-epss
>                - qcom,sa8775p-cpufreq-epss
> 
> -- 
> 2.34.1
> 

Re: [PATCH v5 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible

[Viresh Kumar]

On 11-08-25, 22:46, Bjorn Andersson wrote:
> On Wed, Jul 02, 2025 at 02:43:09PM +0530, Taniya Das wrote:
> > Document compatible for cpufreq hardware on Qualcomm QCS615 platform.
> > 
> 
> @Viresh, @Rafael. Please merge this binding patch through your trees.

Applied. Thanks.

-- 
viresh

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Taniya Das]

On 8/12/2025 9:15 AM, Bjorn Andersson wrote:
> On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
>> Add support for video, camera, display and gpu clock controller nodes
>> for QCS615 platform.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
> 
>   DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> 
> 
> The missing clock-names in clock-controller@100000 predates this series.
> Sorry for merging broken patches in the past, please fix that as well.
> 

Bjorn, would you prefer that I add the clock-names property to the GCC
clock node to resolve the warning, or should I instead remove the
required: clock-names entry from the qcom,qcs615-gcc.yaml schema?

Let me know which approach aligns better with your expectations.

-- 
Thanks,
Taniya Das

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Bjorn Andersson]

On Tue, Aug 12, 2025 at 02:25:12PM +0530, Taniya Das wrote:
> 
> 
> On 8/12/2025 9:15 AM, Bjorn Andersson wrote:
> > On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
> >> Add support for video, camera, display and gpu clock controller nodes
> >> for QCS615 platform.
> >>
> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> >> ---
> > 
> >   DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
> >         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
> >         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
> >         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
> >         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
> >         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> > 
> > 
> > The missing clock-names in clock-controller@100000 predates this series.
> > Sorry for merging broken patches in the past, please fix that as well.
> > 
> 
> Bjorn, would you prefer that I add the clock-names property to the GCC
> clock node to resolve the warning, or should I instead remove the
> required: clock-names entry from the qcom,qcs615-gcc.yaml schema?
> 

It seems to me that the qcs615 gcc binding and driver is lacking a
number of clock inputs. Can you please look into correcting this, and
based on that resolve the dtbs_check error?

Thanks,
Bjorn

> Let me know which approach aligns better with your expectations.
> 
> -- 
> Thanks,
> Taniya Das
> 

Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Taniya Das]

On 8/13/2025 10:50 PM, Bjorn Andersson wrote:
> On Tue, Aug 12, 2025 at 02:25:12PM +0530, Taniya Das wrote:
>>
>>
>> On 8/12/2025 9:15 AM, Bjorn Andersson wrote:
>>> On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
>>>> Add support for video, camera, display and gpu clock controller nodes
>>>> for QCS615 platform.
>>>>
>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>
>>>   DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
>>>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
>>>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
>>>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
>>>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
>>>         from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
>>>
>>>

Bjorn, I will push another series which will fix the above errors.

>>> The missing clock-names in clock-controller@100000 predates this series.
>>> Sorry for merging broken patches in the past, please fix that as well.
>>>
>>
>> Bjorn, would you prefer that I add the clock-names property to the GCC
>> clock node to resolve the warning, or should I instead remove the
>> required: clock-names entry from the qcom,qcs615-gcc.yaml schema?
>>
> 
> It seems to me that the qcs615 gcc binding and driver is lacking a
> number of clock inputs. Can you please look into correcting this, and
> based on that resolve the dtbs_check error?
> 
> 

Yes, Bjorn. I will surely look into to fix them bindings and driver.

> 
>> Let me know which approach aligns better with your expectations.
>>
>> -- 
>> Thanks,
>> Taniya Das
>>

-- 
Thanks,
Taniya Das

Re: (subset) [PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615

[Bjorn Andersson]

On Wed, 02 Jul 2025 14:43:08 +0530, Taniya Das wrote:
> Add the video, camera, display and gpu clock controller nodes and the
> cpufreq-hw node to support cpu scaling.
> 
> Clock Dependency:
> https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com
> 
> Changes in v5:
> - Update the documentation for CPUFREQ-HW for QCS615.
> - Update the device tree node for cpufreq-hw to point to the new compatible.
> - Link to v4: https://lore.kernel.org/r/20250625-qcs615-mm-cpu-dt-v4-v4-0-9ca880c53560@quicinc.com
> 
> [...]

Applied, thanks!

[2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock
      commit: f9c36698db91780eed4ee3a90794bda2a4252166
[3/3] arm64: dts: qcom: qcs615: Add CPU scaling clock node
      commit: fecc6e0b0260279cd1508903db62f370ef4530d4

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>