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Mon, 06 Jan 2025 14:48:49 -0800 (PST) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-842e36caf84sm29367712a12.74.2025.01.06.14.48.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jan 2025 14:48:48 -0800 (PST) Message-ID: <18dbd7d1-a46c-4112-a425-320c99f67a8d@broadcom.com> Date: Mon, 6 Jan 2025 14:48:46 -0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB To: Douglas Anderson , Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Jeffrey Hugo , Trilok Soni , stable@vger.kernel.org, James Morse , Kent Overstreet , Suren Baghdasaryan , linux-kernel@vger.kernel.org References: <20241219205426.2275508-1-dianders@chromium.org> <20241219125317.v3.1.I2040fa004dafe196243f67ebcc647cbedbb516e6@changeid> Content-Language: en-US From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/19/24 12:53, Douglas Anderson wrote: > The code for detecting CPUs that are vulnerable to Spectre BHB was > based on a hardcoded list of CPU IDs that were known to be affected. > Unfortunately, the list mostly only contained the IDs of standard ARM > cores. The IDs for many cores that are minor variants of the standard > ARM cores (like many Qualcomm Kyro CPUs) weren't listed. This led the > code to assume that those variants were not affected. > > Flip the code on its head and instead assume that a core is vulnerable > if it doesn't have CSV2_3 but is unrecognized as being safe. This > involves creating a "Spectre BHB safe" list. > > As of right now, the only CPU IDs added to the "Spectre BHB safe" list > are ARM Cortex A35, A53, A55, A510, and A520. This list was created by > looking for cores that weren't listed in ARM's list [1] as per review > feedback on v2 of this patch [2]. > > NOTE: this patch will not actually _mitigate_ anyone, it will simply > cause them to report themselves as vulnerable. If any cores in the > system are reported as vulnerable but not mitigated then the whole > system will be reported as vulnerable though the system will attempt > to mitigate with the information it has about the known cores. > > [1] https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB > [2] https://lore.kernel.org/r/20241219175128.GA25477@willie-the-truck > > > Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side channels") > Cc: stable@vger.kernel.org > Signed-off-by: Douglas Anderson > --- > > Changes in v3: > - Don't guess the mitigation; just report unknown cores as vulnerable. > - Restructure the code since is_spectre_bhb_affected() defaults to true > > Changes in v2: > - New > > arch/arm64/include/asm/spectre.h | 1 - > arch/arm64/kernel/proton-pack.c | 144 +++++++++++++++++-------------- > 2 files changed, 77 insertions(+), 68 deletions(-) > > diff --git a/arch/arm64/include/asm/spectre.h b/arch/arm64/include/asm/spectre.h > index 0c4d9045c31f..f1524cdeacf1 100644 > --- a/arch/arm64/include/asm/spectre.h > +++ b/arch/arm64/include/asm/spectre.h > @@ -97,7 +97,6 @@ enum mitigation_state arm64_get_meltdown_state(void); > > enum mitigation_state arm64_get_spectre_bhb_state(void); > bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, int scope); > -u8 spectre_bhb_loop_affected(int scope); > void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *__unused); > bool try_emulate_el1_ssbs(struct pt_regs *regs, u32 instr); > > diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c > index da53722f95d4..06e04c9e6480 100644 > --- a/arch/arm64/kernel/proton-pack.c > +++ b/arch/arm64/kernel/proton-pack.c > @@ -845,52 +845,68 @@ static unsigned long system_bhb_mitigations; > * This must be called with SCOPE_LOCAL_CPU for each type of CPU, before any > * SCOPE_SYSTEM call will give the right answer. > */ > -u8 spectre_bhb_loop_affected(int scope) > +static bool is_spectre_bhb_safe(int scope) > +{ > + static const struct midr_range spectre_bhb_safe_list[] = { > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), You can add MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53) here as well. Thanks -- Florian