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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Taniya Das <quic_tdas@quicinc.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>
Cc: Ajit Pandey <quic_ajipan@quicinc.com>,
	Imran Shaik <quic_imrashai@quicinc.com>,
	Jagadeesh Kona <quic_jkona@quicinc.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock
Date: Mon, 3 Feb 2025 15:14:39 +0100	[thread overview]
Message-ID: <19a83d67-7e1a-495b-8dff-e1d2ba05b878@oss.qualcomm.com> (raw)
In-Reply-To: <20250119-qcs615-mm-v2-dt-nodes-v2-1-c46ab4080989@quicinc.com>

On 19.01.2025 1:00 PM, Taniya Das wrote:
> Add support for video, camera, display and gpu clock controller nodes
> for QCS615 platform.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index f4abfad474ea62dea13d05eb874530947e1e8d3e..9d537019437c5202c4d398eecd0ce2a991083175 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -3,7 +3,11 @@
>   * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
> +#include <dt-bindings/clock/qcom,qcs615-camcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
>  #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
> +#include <dt-bindings/clock/qcom,qcs615-videocc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
>  #include <dt-bindings/interconnect/qcom,icc.h>
> @@ -1418,6 +1422,18 @@ data-pins {
>  			};
>  		};
>  
> +		gpucc: clock-controller@5090000 {
> +			compatible = "qcom,qcs615-gpucc";
> +			reg = <0 0x05090000 0 0x9000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GPLL0>;

This would normally be GCC_GPU_GPLL0_(DIV_)CLK_SRC, is this intentional?

Konrad

  reply	other threads:[~2025-02-03 14:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-19 12:00 [PATCH v2 0/2] Add support for clock controllers and CPU scaling for QCS615 Taniya Das
2025-01-19 12:00 ` [PATCH v2 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock Taniya Das
2025-02-03 14:14   ` Konrad Dybcio [this message]
2025-02-04 17:33     ` Taniya Das
2025-02-06 11:42       ` Konrad Dybcio
2025-02-10  9:33         ` Taniya Das
2025-02-10 16:27           ` Konrad Dybcio
2025-01-19 12:00 ` [PATCH v2 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node Taniya Das
2025-02-10 17:58   ` Konrad Dybcio
2025-06-10  9:30     ` Taniya Das
2025-01-23 15:57 ` [PATCH v2 0/2] Add support for clock controllers and CPU scaling for QCS615 Rob Herring (Arm)

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