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Wed, 29 May 2024 23:11:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 44TNBEqi004689 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 May 2024 23:11:14 GMT Received: from [10.71.110.249] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 29 May 2024 16:11:08 -0700 Message-ID: <1ac17233-61ee-6eff-1e28-bd2d74bbc5cc@quicinc.com> Date: Wed, 29 May 2024 16:11:05 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 0/7] drm/msm/dpu: handle non-default TE source pins Content-Language: en-US To: Dmitry Baryshkov CC: Rob Clark , Sean Paul , "Marijn Suijten" , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , , , , References: <20240520-dpu-handle-te-signal-v1-0-f273b42a089c@linaro.org> <9fc7e388-d9c7-12d1-bee5-803dd6f1ca60@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IYhx-57DSdUUVwgrjt2A23p1p9xnQ-CA X-Proofpoint-ORIG-GUID: IYhx-57DSdUUVwgrjt2A23p1p9xnQ-CA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-29_16,2024-05-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405290166 On 5/22/2024 12:59 PM, Dmitry Baryshkov wrote: > On Wed, 22 May 2024 at 21:39, Abhinav Kumar wrote: >> >> >> >> On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote: >>> Command-mode DSI panels need to signal the display controlller when >>> vsync happens, so that the device can start sending the next frame. Some >>> devices (Google Pixel 3) use a non-default pin, so additional >>> configuration is required. Add a way to specify this information in DT >>> and handle it in the DSI and DPU drivers. >>> >> >> Which pin is the pixel 3 using? Just wanted to know .. is it gpio0 or gpio1? > > gpio2. If it was gpio0 then there were no issues at all. > Got it. Instead of asking gpio1 or gpio2, I mistyped and asked gpio0 or gpio1. While reviewing the code , I think the function dpu_hw_setup_vsync_source is poorly named . It really doesnt configured vsync_source. It actually configured watchdog timer. Can you pls include one more patch in this series to rename dpu_hw_setup_vsync_source ---> dpu_hw_setup_wd_timer() >> >>> Signed-off-by: Dmitry Baryshkov >>> --- >>> Dmitry Baryshkov (7): >>> dt-bindings: display/msm/dsi: allow specifying TE source >>> drm/msm/dpu: convert vsync source defines to the enum >>> drm/msm/dsi: drop unused GPIOs handling >>> drm/msm/dpu: pull the is_cmd_mode out of _dpu_encoder_update_vsync_source() >>> drm/msm/dpu: rework vsync_source handling >>> drm/msm/dsi: parse vsync source from device tree >>> drm/msm/dpu: support setting the TE source >>> >>> .../bindings/display/msm/dsi-controller-main.yaml | 16 ++++++++ >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++--- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 5 +-- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 26 ++++++------ >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 2 +- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 44 ++++++++++++++++++++ >>> drivers/gpu/drm/msm/dsi/dsi.h | 1 + >>> drivers/gpu/drm/msm/dsi/dsi_host.c | 48 +++++----------------- >>> drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +++ >>> drivers/gpu/drm/msm/msm_drv.h | 6 +++ >>> 12 files changed, 106 insertions(+), 62 deletions(-) >>> --- >>> base-commit: 75fa778d74b786a1608d55d655d42b480a6fa8bd >>> change-id: 20240514-dpu-handle-te-signal-82663c0211bd >>> >>> Best regards, > > >