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From: Palash Kambar <palash.kambar@oss.qualcomm.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: James.Bottomley@hansenpartnership.com,
	martin.petersen@oracle.com, bvanassche@acm.org,
	shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org,
	linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org,
	nitin.rawat@oss.qualcomm.com
Subject: Re: [PATCH V3 1/2] ufs: core: Configure only active lanes during link
Date: Fri, 17 Apr 2026 09:53:18 +0530	[thread overview]
Message-ID: <1badc187-1fc0-4eaa-90a2-52e7fa172dc0@oss.qualcomm.com> (raw)
In-Reply-To: <i6mbqvrhw2aggbrofp2p6kdhf3jfo4qdmpu72mhhkuqay4i3ua@hcnezixc2vhl>



On 4/16/2026 4:42 PM, Manivannan Sadhasivam wrote:
> On Tue, Apr 14, 2026 at 03:01:34PM +0530, palash.kambar@oss.qualcomm.com wrote:
>> From: Palash Kambar <palash.kambar@oss.qualcomm.com>
>>
>> The number of connected lanes detected during UFS link startup can be
>> fewer than the lanes specified in the device tree. The current driver
>> logic attempts to configure all lanes defined in the device tree,
>> regardless of their actual availability. This mismatch may cause
>> failures during power mode changes.
>>
>> Hence, Add a check during link startup to ensure that only the lanes
>> actually discovered are considered valid. If a mismatch is detected,
>> fail the initialization early, preventing the driver from entering
>> an unsupported configuration that could cause power mode transition
>> failures.
>>
>> Signed-off-by: Palash Kambar <palash.kambar@oss.qualcomm.com>
>> ---
>>  drivers/ufs/core/ufshcd.c | 37 +++++++++++++++++++++++++++++++++++++
>>  1 file changed, 37 insertions(+)
>>
>> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
>> index 31950fc51a4c..754bf4df3016 100644
>> --- a/drivers/ufs/core/ufshcd.c
>> +++ b/drivers/ufs/core/ufshcd.c
>> @@ -5035,6 +5035,38 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
>>  }
>>  EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
>>  
>> +static int ufshcd_validate_link_params(struct ufs_hba *hba)
>> +{
>> +	int ret;
>> +	int val;
> 
> ret, val
> 
>> +
>> +	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
>> +			     &val);
>> +	if (ret)
>> +		goto out;
>> +
>> +	if (val != hba->lanes_per_direction) {
>> +		dev_err(hba->dev, "Tx lane mismatch [config,reported] [%d,%d]\n",
>> +			hba->lanes_per_direction, val);
>> +		ret = -ENOLINK;
>> +		goto out;
>> +	}
>> +
>> +	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
>> +			     &val);
>> +	if (ret)
>> +		goto out;
>> +
>> +	if (val != hba->lanes_per_direction) {
>> +		dev_err(hba->dev, "Rx lane mismatch [config,reported] [%d,%d]\n",
>> +			hba->lanes_per_direction, val);
>> +		ret = -ENOLINK;
> 
> 		goto out;
> 
>> +	}
>> +
> 
> return 0;
> 
>> +out:
>> +	return ret;
>> +}
>> +
>>  /**
>>   * ufshcd_link_startup - Initialize unipro link startup
>>   * @hba: per adapter instance
>> @@ -5108,6 +5140,11 @@ static int ufshcd_link_startup(struct ufs_hba *hba)
>>  			goto out;
>>  	}
>>  
>> +	/* Check successfully detected lanes */
> 
> Drop the comment.

Will update as per suggestion.
Thanks.
> 


  reply	other threads:[~2026-04-17  4:23 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-14  9:31 [PATCH V3 0/2] Add post change sequence for link start notify palash.kambar
2026-04-14  9:31 ` [PATCH V3 1/2] ufs: core: Configure only active lanes during link palash.kambar
2026-04-16 11:12   ` Manivannan Sadhasivam
2026-04-17  4:23     ` Palash Kambar [this message]
2026-04-14  9:31 ` [PATCH V3 2/2] ufs: ufs-qcom: Enable Auto Hibern8 clock request support palash.kambar
2026-04-16 11:13   ` Manivannan Sadhasivam

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