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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc7627fa7sm562549666b.38.2026.02.19.01.58.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Feb 2026 01:58:50 -0800 (PST) Message-ID: <1c43591f-ffc3-433e-94b2-8cc7bdb3ec62@oss.qualcomm.com> Date: Thu, 19 Feb 2026 10:58:48 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths To: webgeek1234@gmail.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> <20260218-sm8550-ddr-bw-scaling-v2-3-43a2b6d47e70@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=ceffb3DM c=1 sm=1 tr=0 ts=6996dedc cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=XEhIh8xtOs_--jVvVqkA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: X8MgVLW9auS4WUAEProeL_w8a2tqI8Gg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDA5MSBTYWx0ZWRfX9F5/AsxuKCKw cOuCw0o7ZIlns3QFbV0Sy78f+h+pctg3aaFD1bnWzl/oa+MY6mqxDPJWraz/WlbZ16EDpvx7fZi MUbMxzIqpVPodXklkM7V+N2pyCIkjIj7cVyz7tk/fjGe88+KC6NnSOfBFwID08IiuasJwzy4WdT iMpVRtTSgGXqwbDyHgdXCTlcDRnJACswolGKSVaQJR88aJE+4Eubs6dgRhWZJIyFKEp71Fn18O1 BBewnhS1V+W9YZcwQ1eVY6mmGG4G7g29sR3hJlJn/dxscwxxZURZg0U6OLXWDcxmYfo4K7P9vyY pxE55PB1PwG3RHxxdHbmyt5qe1qhQZzCvV7o7r13dmZktcsZ9w2nREeeCaTnRWUTq3+g88TnCd2 5po2N/p2L+Tsi4eCeOdmSEOGqVAm7bzMSDZxIfowBJK3Nl3vPBKN1BXaOYLT8PcZVgPJC8Btato nXRJWPRz/Yu99sJomWA== X-Proofpoint-ORIG-GUID: X8MgVLW9auS4WUAEProeL_w8a2tqI8Gg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_03,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602190091 On 2/19/26 10:57 AM, Konrad Dybcio wrote: > On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote: >> From: Aaron Kling >> >> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) >> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache >> frequency by aggregating bandwidth requests of all CPU core with referenc >> to the current OPP they are configured in by the LMH/EPSS hardware. >> >> The effect is a proper caches & DDR frequency scaling when CPU cores >> changes frequency. >> >> The OPP tables were built using the downstream memlat ddr, llcc & l3 >> tables for each cluster types with the actual EPSS cpufreq LUT tables >> from running a QCS8550 device. >> >> Signed-off-by: Aaron Kling >> --- > > Once squashed: > > Reviewed-by: Konrad Dybcio FYI I did notice a couple of "trip points" in the downstream DT that refer to higher than described (i.e. >3 GHz) OPPs, but I can't find data about them internally. Anyway, this is good and if someone has a "very fast 8550", we can always extend that Konrad