Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 9/14/25 5:57 PM, Xilin Wu wrote:
> Add and enable all available QUP SEs on this board, allowing I2C, SPI and
> UART functions from the 40-Pin GPIO header to work.
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> 
> ---
> 
> This change depends on the following patch series:
> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/

You should be good to go resending this change now, the series is in> ---
>  .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 66 ++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> index 85465702279efb7ab324baea0663bdbdbd5fb5ac..d30cddfc3eff07237c7e3480a5d42b29091d87d6 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> @@ -432,6 +432,14 @@ &gcc {
>  			   <GCC_WPSS_RSCP_CLK>;
>  };
>  
> +&gpi_dma0 {
> +	status = "okay";
> +};
> +
> +&gpi_dma1 {
> +	status = "okay";
> +};
> +
>  &gpu {
>  	status = "okay";
>  };
> @@ -440,6 +448,40 @@ &gpu_zap_shader {
>  	firmware-name = "qcom/qcs6490/a660_zap.mbn";
>  };
>  
> +/* Pin 13, 15 in GPIO header */
> +&i2c0 {
> +	qcom,enable-gsi-dma;
> +	status = "okay";

Please leave a spare \n before status, otherwise lgtm

Konrad