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Mon, 08 Apr 2024 19:09:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 438J9CBG028387 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 8 Apr 2024 19:09:12 GMT Received: from [10.110.52.150] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 8 Apr 2024 12:09:12 -0700 Message-ID: <1d6911e2-d0ec-4cb0-b417-af5001a4f8a3@quicinc.com> Date: Mon, 8 Apr 2024 12:09:11 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 1/2] dt-bindings: pcie: Document QCOM PCIE ECAM compatible root complex Content-Language: en-US To: Krzysztof Kozlowski , , , , , , , , , , CC: , , , , , References: <1712257884-23841-1-git-send-email-quic_mrana@quicinc.com> <1712257884-23841-2-git-send-email-quic_mrana@quicinc.com> <51b02d02-0e20-49df-ad13-e3dbe3c3214f@linaro.org> From: Mayank Rana In-Reply-To: <51b02d02-0e20-49df-ad13-e3dbe3c3214f@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pQgWknvelri6Ti57XfXZ4X23az7toq-f X-Proofpoint-ORIG-GUID: pQgWknvelri6Ti57XfXZ4X23az7toq-f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-08_16,2024-04-05_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 clxscore=1015 spamscore=0 impostorscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404080148 Hi Krzysztof On 4/4/2024 12:30 PM, Krzysztof Kozlowski wrote: > On 04/04/2024 21:11, Mayank Rana wrote: >> On some of Qualcomm platform, firmware configures PCIe controller in RC > > On which? > > Your commit or binding must answer to all such questions. > >> mode with static iATU window mappings of configuration space for entire >> supported bus range in ECAM compatible mode. Firmware also manages PCIe >> PHY as well required system resources. Here document properties and >> required configuration to power up QCOM PCIe ECAM compatible root complex >> and PHY for PCIe functionality. >> >> Signed-off-by: Mayank Rana >> --- >> .../devicetree/bindings/pci/qcom,pcie-ecam.yaml | 94 ++++++++++++++++++++++ >> 1 file changed, 94 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml >> new file mode 100644 >> index 00000000..c209f12 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml >> @@ -0,0 +1,94 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/qcom,pcie-ecam.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm ECAM compliant PCI express root complex >> + >> +description: | > Do not need '|' unless you need to preserve formatting. ACK > >> + Qualcomm SOC based ECAM compatible PCIe root complex supporting MSI controller. > > Which SoC? ACK >> + Firmware configures PCIe controller in RC mode with static iATU window mappings >> + of configuration space for entire supported bus range in ECAM compatible mode. >> + >> +maintainers: >> + - Mayank Rana >> + >> +allOf: >> + - $ref: /schemas/pci/pci-bus.yaml# >> + - $ref: /schemas/power-domain/power-domain-consumer.yaml >> + >> +properties: >> + compatible: >> + const: qcom,pcie-ecam-rc > > No, this must have SoC specific compatibles. This driver is proposed to work with any PCIe controller supported ECAM functionality on Qualcomm platform where firmware running on other VM/processor is controlling PCIe PHY and controller for PCIe link up functionality. Do you still suggest to have SoC specific compatibles here ? >> + >> + reg: >> + minItems: 1 > > maxItems instead > >> + description: ECAM address space starting from root port till supported bus range >> + >> + interrupts: >> + minItems: 1 >> + maxItems: 8 > > This is way too unspecific. will review and update. >> + >> + ranges: >> + minItems: 2 >> + maxItems: 3 > > Why variable? It depends on how ECAM configured to support 32-bit and 64-bit based prefetch address space. So there are different combination of prefetch (32-bit or 64-bit or both) and non-prefetch (32-bit), and IO address space available. hence kept it as variable with based on required use case and address space availability. >> + >> + iommu-map: >> + minItems: 1 >> + maxItems: 16 > > Why variable? > > Open existing bindings and look how it is done. ok. will review and update as needed. > >> + >> + power-domains: >> + maxItems: 1 >> + description: A phandle to node which is able support way to communicate with firmware >> + for enabling PCIe controller and PHY as well managing all system resources needed to >> + make both controller and PHY operational for PCIe functionality. > > This description does not tell me much. Say something specific. And drop > redundant parts like phandle. ok. will rephrase it. > >> + >> + dma-coherent: true >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - ranges >> + - power-domains >> + - device_type >> + - linux,pci-domain >> + - bus-range >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + pcie0: pci@1c00000 { >> + compatible = "qcom,pcie-ecam-rc"; >> + reg = <0x4 0x00000000 0 0x10000000>; >> + device_type = "pci"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0x0 0x40000000 0x0 0x40000000 0x0 0x100000>, >> + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, >> + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x100000>; > > Follow DTS coding style about placement and alignment. > > Best regards, > Krzysztof > Regards, Mayank