From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v1 1/2] iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1 Date: Mon, 4 Aug 2014 10:41:55 +0100 Message-ID: <20140804094155.GC15117@arm.com> References: <1407113264-23426-1-git-send-email-ohaugan@codeaurora.org> <1407113264-23426-2-git-send-email-ohaugan@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1407113264-23426-2-git-send-email-ohaugan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Olav Haugan Cc: "linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: linux-arm-msm@vger.kernel.org Hi Olav, On Mon, Aug 04, 2014 at 01:47:43AM +0100, Olav Haugan wrote: > Stage-1 context bank does not have SMMU_CBn_TCR[SL0] field. SL0 field > is only applicable to stage-2 context banks. Ha, I actually noticed this last week but didn't get around to writing a a fix. Thanks for taking a look! > Signed-off-by: Olav Haugan > --- > drivers/iommu/arm-smmu.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index ff6633d..a83ca6a 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -833,6 +833,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) > reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); > break; > } > + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); > + I think this block is all predicated on smmu->version > 1, so we need something for stage2 CBs on SMMUv1 too. Will