From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lina Iyer Subject: Re: [PATCH v2 07/10] qcom: msm-pm: Add cpu low power mode functions Date: Thu, 14 Aug 2014 08:43:33 -0600 Message-ID: <20140814144332.GA33559@ilina-mac.local> References: <1407872640-6732-1-git-send-email-lina.iyer@linaro.org> <1407872640-6732-8-git-send-email-lina.iyer@linaro.org> <53ECBBCD.6050006@smartplayin.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Return-path: Received: from mail-pa0-f42.google.com ([209.85.220.42]:36115 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751521AbaHNOnk (ORCPT ); Thu, 14 Aug 2014 10:43:40 -0400 Received: by mail-pa0-f42.google.com with SMTP id lf10so1758171pab.15 for ; Thu, 14 Aug 2014 07:43:39 -0700 (PDT) Content-Disposition: inline In-Reply-To: <53ECBBCD.6050006@smartplayin.com> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Pramod Gurav Cc: daniel.lezcano@linaro.org, khilman@linaro.org, amit.kucheria@linaro.org, sboyd@codeaurora.org, davidb@codeaurora.org, galak@codeaurora.org, linux-arm-msm@vger.kernel.org, msivasub@codeaurora.org, Venkat Devarasetty On Thu, Aug 14, 2014 at 07:08:21PM +0530, Pramod Gurav wrote: >On Wednesday 13 August 2014 01:13 AM, Lina Iyer wrote: >> Add interface layer to abstract and handle hardware specific >> functionality for executing various cpu low power modes in QCOM >> chipsets. >> >> Signed-off-by: Venkat Devarasetty >> Signed-off-by: Mahesh Sivasubramanian >> Signed-off-by: Lina Iyer >> --- >> drivers/soc/qcom/Makefile | 2 +- >> drivers/soc/qcom/msm-pm.c | 219 ++++++++++++++++++++++++++++++++++++++++++++++ >> include/soc/qcom/pm.h | 39 +++++++++ > > > >> +{ >> + u32 cache_id = 0; >> + >> +#if defined(CONFIG_CPU_V7) >> + u32 sel = 0; >> + >> + asm volatile ("mcr p15, 2, %[ccselr], c0, c0, 0\n\t" >> + "isb\n\t" >> + "mrc p15, 1, %[ccsidr], c0, c0, 0\n\t" >> + :[ccsidr]"=r" (cache_id) >> + :[ccselr]"r" (sel) > >Space after ':' is what checkpatch asks. :) See below > >> + ); >> + return cache_id & BIT(30); >> +#elif defined(CONFIG_ARM64) >> + u32 sel = 0; > >new line missing after declaration. Ok. > >> + asm volatile("msr csselr_el1, %[ccselr]\n\t" >> + "isb\n\t" >> + "mrs %[ccsidr],ccsidr_el1\n\t" >> + :[ccsidr]"=r" (cache_id) >> + :[ccselr]"r" (sel) > >Space after ':' is what checkpatch asks. :) Yes, checkpatch seems to complain eitherways, whether you have a space or not. The advice was to ignore it. > >> + ); >> + return cache_id & BIT(30); >> +#else >> +#error No valid CPU arch selected >> +#endif >> +} >> + > >>